AT91SAM7SE256-CU Atmel, AT91SAM7SE256-CU Datasheet - Page 49

• Manufacturer Part Number: AT91SAM7SE256-CU
• Description: IC ARM7 MCU FLASH 256K 144-LFBGA
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91SAM7SE256-CU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 55MHz
• Connectivity: EBI/EMI, I²C, SPI, SSC, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 88
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 1.95 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 144-LFBGA
• Processor Series: AT91SAMx
• Core: ARM7TDMI
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: EBI, SPI, TWI, USART
• Maximum Clock Frequency: 48 MHz
• Number Of Programmable I/os: 32
• Number Of Timers: 3
• Operating Supply Voltage: 1.8 V to 3.3 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, KSK-AT91SAM7S-PL, MDK-ARM, RL-ARM, ULINK2
• Development Tools By Supplier: AT91SAM-ICE, AT91-ISP, AT91SAM7SE-EK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit
• For Use With: AT91SAM7SE-EK - EVAL BOARD FOR AT91SAM7SEAT91SAM-ICE - EMULATOR FOR AT91 ARM7/ARM9
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Details
• Other names: AT91SAM7SE256-CJ; AT91SAM7SE256-CJ

12. Debug and Test Features
12.1
12.2
6222F–ATARM–14-Jan-11
Overview
Block Diagram
The SAM7SE Series Microcontrollers feature a number of complementary debug and test capa-
bilities. A common JTAG/ICE (Embedded ICE) port is used for standard debugging functions,
such as downloading code and single-stepping through programs. The Debug Unit provides a
two-pin UART that can be used to upload an application into internal SRAM. It manages the
interrupt handling of the internal COMMTX and COMMRX signals that trace the activity of the
Debug Communication Channel.
A set of dedicated debug and test input/output pins gives direct access to these capabilities from
a PC-based test environment.
Figure 12-1. Debug and Test Block Diagram
PDC
Boundary
ARM7TDMI
TAP
DBGU
ICE
ICE/JTAG
SAM7SE512/256/32 Preliminary
TAP
Reset
Test
and
POR
JTAGSEL
TDO
TMS
TCK
TDI
DTXD
DRXD
TST
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