MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 1052
MPC564CZP40
Manufacturer Part Number
MPC564CZP40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564CZP40
Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC564CZP40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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READI Module
DSDI message fields of the development port access message are explained in
DSDO message fields of the development port access message are explained in
24-84
.
1
2
Start
Ready
The “Freeze” status is set to (1) when the CPU is in debug mode and to (0) otherwise.
The “Download Procedure in progress” status is asserted (0) when Debug port in the Download procedure and is
negated (1) otherwise.
(0)
(0)
(0)
(0)
1
1
1
1
1
Header
Mode
Header
0
0
1
1
1
0
0
1
1
Status [0:1]
Control
0
1
0
1
1
0
1
0
1
Table 24-34. Development Port Access: DSDO Field
Table 24-33. Development Port Access: DSDI Field
Trap enable
0011111
Bits 0:6
MPC561/MPC563 Reference Manual, Rev. 1.2
Freeze
status
0
Bit 0
1
Instruction / Data (32 Bits)
Procedure
Download
progress
CPU Instruction
Bit 1
in
CPU Data
Data
2
Does not exist
Does not exist
Does not exist
Data
Data
(Depending on Input Mode)
Bits 7:31
Bits 2:31 or 2:6 —
1’s
1’s
1’s
Negate breakpoint requests
Table
Table
Transfer Instruction
Valid Data from CPU
Sequencing Error
CPU Interrupt
Null
Control Register
Transfer data to
Transfer Data
Trap Enable
to the CPU.
Freescale Semiconductor
Function
24-33.
to CPU
to CPU
24-34.
NOP
Function
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