MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 370
MPC564CZP40
Manufacturer Part Number
MPC564CZP40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564CZP40
Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC564CZP40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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External Bus Interface
The MPC561/MPC563 performs operand transfers through its 32-bit data port. If the transfer is controlled
by the internal memory controller, the MPC561/MPC563 can support 8- and 16-bit data port sizes.
The bus requires that the portion of the data bus used for a transfer to or from a particular port size be fixed.
A 32-bit port resides on DATA[0:31], a 16-bit port must reside on DATA[0:15], and an 8-bit port must
reside on DATA[0:7]. The MPC561/MPC563 always tries to transfer the maximum amount of data on all
bus cycles. For a word operation, it always assumes that the port is 32 bits wide when beginning the bus
cycle.
In
9-30
Figure
•
•
•
•
•
Word accesses require address bits 30 – 31 to equal zero
Burst accesses require address bits 30 – 31 to equal zero
OP0 is the most-significant byte of a word operand and OP3 is the least-significant byte.
The two bytes of a half-word operand are either OP0 (most-significant) and OP1 or OP2
(most-significant) and OP3, depending on the address of the access.
The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on the address of
the access.
9-22,
0
Figure
OP0
OP0
OP0
9-23,
Table
Figure 9-22. Internal Operand Representation
MPC561/MPC563 Reference Manual, Rev. 1.2
OP1
OP1
OP1
9-2, and
Table
OP2
OP2
OP2
9-3, the following conventions are used:
OP3
OP3
OP3
31
Word
Half-word
Byte
Freescale Semiconductor
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