MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 520

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

QADC64E Legacy Mode Operation
In situation S2
trigger event is complete, the trigger overrun bit is again set, but otherwise, the additional trigger events
are ignored. After the queue is complete, the first newly detected trigger event causes queue execution to
begin again. When the trigger event rate is high, a new trigger event can be seen very soon after completion
of the previous queue, leaving software little time to retrieve the previous results. Also, when trigger events
are occurring at a high rate for queue 1, the lower priority queue 2 channels may not get serviced at all.
Situation S3
is set the same way, and that queue execution continues unchanged.
13-56
Q1
Q2
QS
QS
Q1
Q2
IDLE
Q1:
T1 T1
(Figure
C1
TOR1
(Figure
IDLE
0000
ACTIVE
C2
TOR1
T1
13-28) shows that when the pause feature is in use, the trigger overrun error status bit
1000
13-27), more than one trigger event is recognized before servicing of a previous
C3
TOR1
T1
Q1:
C4
T1
CF1
IDLE
IDLE
C1
IDLE
MPC561/MPC563 Reference Manual, Rev. 1.2
Figure 13-27. CCW Priority Situation 1
Figure 13-28. CCW Priority Situation 2
TOR1
T1
T1
ACTIVE
C2
C1
1000
C3
ACTIVE
C2
1000
C4
C3
CF1
C4
0000
CF1
Q2:
T2
C1
0000
ACTIVE
C2
Q2:
T2
TOR2
0010
T2
IDLE
C3
IDLE
C1
TOR2
C4
T2
C2
ACTIVE
CF2
0010
TOR2
C3
T2
Freescale Semiconductor
IDLE
C4
0000
CF2
IDLE
0000
QADC S2
QADC S1