MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 1098
MPC564CZP40
Manufacturer Part Number
MPC564CZP40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564CZP40
Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
MPC564CZP40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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MPC562/MPC564 Compression Features
Alternatives #1 and #2 are referred to as CLASS_2a and CLASS_2b respectively.
A.2.9.4
For the MPC562/MPC564, the instruction is divided into two segments. The left segment is compressed
and mapped into a vocabulary. The vocabulary location is programmable. The right segment is either fully
bypassed by a 16-bit field or by a shorter field which is decompressed according to fixed rules.
The definition of the class includes
When the vocabulary is located in RAM #1, the class will be referred to as CLASS_3a and when the
vocabulary is located in RAM #2, the class will be referred to as CLASS_3b.
A-10
.
MSB
•
•
•
•
•
•
•
•
•
•
•
16-bit segment #1 – to be compressed
4-bit class
TP1 length=2-9
TP2 length=2-9
AS=0
For alternative #1:
— TP1 base address = base address of segment #1 vocabulary in RAM #1
— TP2 base address = base address of segment #2 vocabulary in RAM #2
— DS=0
For alternative #2:
— TP1 base address = base address of segment #2 vocabulary in RAM #1
— TP2 base address = base address of segment #1 vocabulary in RAM #2
— DS=1
TP1 length=2-9
TP2 length=0xB, 0xC, 0xD, or 0xE indicating a 0, 10, 15 or 16 bit bypass, respectively.
TP1 base address = base address of segment #1 vocabulary in RAM #1, if it exists there.
TP2 base address = base address of segment #1 vocabulary in RAM #2, if it exists there.
DS=0
AS=0 or 1 directing access to the vocabulary in RAM #1 or RAM #2, respectively.
Left Segment Compression and Right Segment Bypass – CLASS_3
2- to 9-bit TP1 for segment #1
Figure A-9. CLASS_3 Instruction Layout
MPC561/MPC563 Reference Manual, Rev. 1.2
Uncompressed Instruction
Compressed Instruction
16-bit segment #2 – to be bypassed
0-, 10-, 15- or 16-bit bypass for segment #2
Freescale Semiconductor
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