MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 177

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Note: The dot (.) suffix on a mnemonic indicates that the CR register update is enabled. The o suffix on a mnemonic indicates
3.10.2
To simplify assembly language coding, a set of alternative mnemonics is provided for some frequently
used operations (such as no-op, load immediate, load address, move register, and complement register).
Freescale Semiconductor
sthbrx
sthu
sthux
sthx
stmw
stswi
stswx
stw
stwbrx
stwcx.
stwu
stwux
stwx
subf (subf. subfo subfo.)
subfc (subfc. subfco subfco.)
subfe (subfe. subfeo subfeo.)
subfic
subfme (subfme. subfmeo subfmeo.)
subfze (subfze. subfzeo subfzeo.)
sync
tw
twi
xor (xor.)
xori
xoris
that the overflow bit update in the XER is enabled.
Recommended Simplified Mnemonics
Mnemonic
Table 3-17. Instruction Set Summary (continued)
MPC561/MPC563 Reference Manual, Rev. 1.2
rS,rA,rB
rS,d(rA)
rS,rA,rB
rS,rA,rB
rS,d(rA)
rS,rA,NB
rS,rA,rB
rS,d(rA)
rS,rA,rB
rS,rA,rB
rS,d(rA)
rS,rA,rB
rS,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,SIMM
rD,rA
rD,rA
TO,rA,rB
TO,rA,SIMM
rA,rS,rB
rA,rS,UIMM
rA,rS,UIMM
Operand Syntax
—
Store Half-Word Byte-Reverse Indexed
Store Half-Word with Update
Store Half-Word with Update Indexed
Store Half-Word Indexed
Store Multiple Word
Store String Word Immediate
Store String Word Indexed
Store Word
Store Word Byte-Reverse Indexed
Store Word Conditional Indexed
Store Word with Update
Store Word with Update Indexed
Store Word Indexed
Subtract From
Subtract from Carrying
Subtract from Extended
Subtract from Immediate Carrying
Subtract from Minus One Extended
Subtract from Zero Extended
Synchronize
Trap Word
Trap Word Immediate
XOR
XOR Immediate
XOR Immediate Shifted
Name
Central Processing Unit
3-33