MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 222

• Manufacturer Part Number: MPC564CZP40
• Description: IC MPU 32BIT W/CODE COMP 388PBGA
• Manufacturer: Freescale Semiconductor
• Series: MPC5xxr

Specifications of MPC564CZP40

• Core Processor: PowerPC
• Core Size: 32-Bit
• Speed: 40MHz
• Connectivity: CAN, EBI/EMI, SCI, SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 56
• Program Memory Size: 512KB (512K x 8)
• Program Memory Type: FLASH
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 2.7 V
• Data Converters: A/D 32x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 388-BGA
• Processor Series: MPC5xx
• Core: PowerPC
• Data Bus Width: 32 bit
• Data Ram Size: 32 KB
• Interface Type: CAN, JTAG, QSPI, SCI, SPI, UART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 56
• Number Of Timers: 2
• Operating Supply Voltage: 0 V to 5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 2 (10 bit, 32 Channel)
• For Use With: MPC564EVB - KIT EVAL FOR MPC561/562/563/564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: No

Burst Buffer Controller 2 Module
4.5.1.1
Write access to any BBC special purpose register invalidates all BTB entries.
4.5.1.2
The BTB operation may be enabled or disabled by programming the BTEE bit in the BBCMCR register.
4.5.1.3
The BTB operation may be inhibited regarding some memory regions. The BTB caching is inhibited for
a region if the BTBINH bit is set in the region attribute register (or global region attribute register). See
4-16
Next Address
Next Address
Next Address
Next Address
Next Address
Next Address
Next Address
Next Address
Tag Register/Comparator
Tag Register/Comparator
Tag Register/Comparator
Tag Register/Comparator
Tag Register/Comparator
Tag Register/Comparator
Tag Register/Comparator
Tag Register/Comparator
BTE TAG Register File
BTB Invalidation
BTB Enabling/Disabling
BTB Inhibit Regions
To guarantee that the BTB does not contain instructions that may have been
changed, the BTB contents should be invalidated any time instruction
memory is modified.
32-bit
Instruction
Address
VDC
VDC
VDC
VDC
VDC
VDC
VDC
VDC
MPC561/MPC563 Reference Manual, Rev. 1.2
V
V
V
V
V
V
V
V
Figure 4-5. BTB Block Diagram
Hit
Hit
Hit
Hit
Hit
Hit
Hit
Hit
NOTE
BTB Hit
BTE Memory Array
Instruction Buffers
Instruction Buffers
Instruction Buffers
Instruction Buffers
Instruction Buffers
Instruction Buffers
Instruction Buffers
Instruction Buffers
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