MPC564CZP40 Freescale Semiconductor, MPC564CZP40 Datasheet - Page 519
MPC564CZP40
Manufacturer Part Number
MPC564CZP40
Description
IC MPU 32BIT W/CODE COMP 388PBGA
Manufacturer
Freescale Semiconductor
Series
MPC5xxr
Specifications of MPC564CZP40
Core Processor
PowerPC
Core Size
32-Bit
Speed
40MHz
Connectivity
CAN, EBI/EMI, SCI, SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
56
Program Memory Size
512KB (512K x 8)
Program Memory Type
FLASH
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
2.5 V ~ 2.7 V
Data Converters
A/D 32x10b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
388-BGA
Processor Series
MPC5xx
Core
PowerPC
Data Bus Width
32 bit
Data Ram Size
32 KB
Interface Type
CAN, JTAG, QSPI, SCI, SPI, UART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
56
Number Of Timers
2
Operating Supply Voltage
0 V to 5 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
2 (10 bit, 32 Channel)
For Use With
MPC564EVB - KIT EVAL FOR MPC561/562/563/564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Eeprom Size
-
Lead Free Status / Rohs Status
No
Available stocks
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Part Number
Manufacturer
Quantity
Price
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Part Number:
MPC564CZP40
Manufacturer:
Freescale Semiconductor
Quantity:
10 000
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When a trigger event causes a CCW execution in progress to be aborted, the aborted conversion is shown
as a ragged end of a shortened CCW rectangle.
The situation diagrams also show when key status bits are set.
Below the queue execution flows are three sets of blocks that show the status information that is made
available to the software. The first two rows of status blocks show the condition of each queue as:
The third row of status blocks shows the 4-bit QS status register field that encodes the condition of the two
queues. Two transition status cases, QS = 0011 and QS = 0111, are not shown because they exist only very
briefly between stable status conditions.
The first three examples in
a new trigger event is recognized before the queue has completed servicing the previous trigger event on
the same queue.
In situation S1
working on the previously recognized trigger event. The trigger overrun error status bit is set, and
otherwise, the premature trigger event is ignored. A trigger event that occurs before the servicing of the
previous trigger event is completed does not disturb the queue execution in progress.
Freescale Semiconductor
•
•
•
•
•
Trigger Overrun
Idle
Active
Pause
Suspended (queue 2 only)
Trigger pending
Error (TOR)
CF Flag
PF Flag
Bit
(Figure
13-27), one trigger event is being recognized on each queue while that queue is still
Set when the end of the queue is reached
Set when a queue completes execution up through a pause bit
Set when a new trigger event occurs before the queue is finished serving the previous trigger
event
Figure 13-27
MPC561/MPC563 Reference Manual, Rev. 1.2
through
Table 13-23. Status Bits
Figure 13-29
Function
(S1, S2, and S3) show what happens when
Table 13-23
describes the status bits.
QADC64E Legacy Mode Operation
13-55
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