BGW200EG/01,518 NXP Semiconductors, BGW200EG/01,518 Datasheet
BGW200EG/01,518
Specifications of BGW200EG/01,518
BGW200EG/01-T
BGW200EG/01-T
Related parts for BGW200EG/01,518
BGW200EG/01,518 Summary of contents
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BGW200EG IEEE 802.11b System-in-Package Rev. 01 — 18 July 2007 1. General description The BGW200EG is a plug-and-play System-in-Package (SiP) for IEEE Std 802.11b - 1999 Wireless Local Area Network (WLAN) intended for embedded and mobile applications. The BGW200EG comprises ...
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... Data rates Mbit/s N WEP, TKIP, CCM and AES encryption and decryption engines I Bluetooth coexistence interface: N Interfaces to a range of NXP Semiconductors Bluetooth modules N Hardware functionality to facilitate connection to 3rd-party Bluetooth solutions N Hardware support for IEEE 802.15.2 packet traffic arbitration recommendations I Embedded 32-bit microcontroller: ...
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... NXP Semiconductors 2.5 Software I Microcontroller firmware I IEEE 802.11b/e/i protocol firmware (see I WPA and WMM1 protocol firmware (see I Host drivers for the following operating systems: N WinCE 4.2/5.0 N Embedded Linux I Configuration utility 2.6 Reference I The MAC implemented in the SA2443A is fully compliant with the relevant parts of the published IEEE 802 ...
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SA2405 RF TRANSCEIVER BGW200EG SA2411 PA upmixers PA PA drivers ANTENNA SWITCH SYNTHESIZER LNA downmixers Fig 1. Block diagram 3-WIRE INTERFACE TXI FIR DAC baseband filters TXQ FIR DAC AGC STATE MACHINE RSSI RF VCO A D RSSI RXI A ...
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... NXP Semiconductors 6. Pinning information 6.1 Pinning Fig 2. Pin configuration BGW200EG_1 Product data sheet land 1 index area 1 GND GND 2 TEST_RSSI 3 4 GND GND V 5 DDA(VCO) GND 6 GND 7 8 TEST_LOCK GND 9 BGW200EG/01 OSC_B 10 GND OSC_E 11 12 GND REFCLK_OUT 13 MODE2 DDA 16 V DDD(IO) n ...
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... NXP Semiconductors 6.2 Pin description Table 2. Pin description Symbol Pin Type SPI interface SPI_SCK 25 I/O; I SPI_SS_N 27 I; I/O SPI_EXT_INT 24 O; I/O SPI_MISO 26 I/O SPI_MOSI 28 I/O SDIO Interface SD_CLK SD_CMD 36 I/O SD_DAT0 38 I/O SD_DAT1 39 I/O SD_DAT2 34 I/O SD_DAT3 35 I/O UART interface UART_RX 40 I ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin Type TEST_AGCRESET 64 O REFCLK_OUT 13 O Bluetooth coexistence interface GPIO0 I/O 3-state slew rate; GPIO1 51 I; I/O GPIO2 50 I; I/O GPIO3 49 O; I/O GPIO interface GPIO9 32 I/O GPIO10 33 I/O JTAG and debug interface JTAG_TCLK ...
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... NXP Semiconductors Table 2. Pin description …continued Symbol Pin Type MODE3 30 - MODE4 Power supplies DDA(VCO DDA DDD(IO DDD( DD(PA DD(DRIVER DDA(RF) GND 1 - GND 2 - GND 4 - GND 6 - GND 7 - GND 9 - GND 12 - GND 48 - GND 54 - GND 56 - GND 58 - GND 61 - GND 62 - GND 65 - GND 67 - GND input mode. [2] The RST_N pin should be linked to the POR_N pin; use of an external reset signal is not supported. ...
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... NXP Semiconductors 7. Functional description 7.1 General The BGW200EG contains the following parts in one SiP (with embedded software): • IEEE 802.11b RF transceiver • IEEE 802.11b compliant modem • IEEE 802.11b MAC • ARM7TDMI-S microcontroller • Static RAM (SRAM) • Interface circuits • ...
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... NXP Semiconductors will be the basis for smart phones and PDAs to communicate with a LAN network through a WLAN access point both for voice (VoIP) and data access designed to handle the IEEE 802.11b specification. The BGW200EG combines the IEEE 802.11b PHY and MAC with the embedded HCI fi ...
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... NXP Semiconductors Table 3. Block name MAC: HW MAC PHYTX PHYRX WEP AES (CCM) DMA RFIF TIMERS ICU UART SPI: SPI1 SPI2 SDIO GPIO 8. SA2405 RF transceiver The SA2405 RF transceiver is targeted for operation in the 2.45 GHz band, specifically for IEEE 802.11b 1 Mbit/s and 2 Mbit/s DSSS, and 5.5 Mbit/s and 11 Mbit/s CCK high rate standards ...
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... NXP Semiconductors After the AGC settling (may be more than one AGC cycle with antenna diversity), the high-pass is configured to 100 kHz for 5 s before switching to a final 10 kHz cut-off frequency. The low value of 10 kHz is required for minimizing the signal distortion created by a high-pass function at zero frequency ...
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... NXP Semiconductors Upon entering the TX mode, the ramping-up of the RF TX signal is delayed by an internal power ramping circuit. The ramping-up time is fixed while the delay prior to ramping-up can be programmed by register settings. There gain control with 1 dB resolution. A gain adjustment range steps is provided in the TX reconstruction fi ...
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... NXP Semiconductors The SA2443A has five reset sources: • External reset (pin RST_N) • Watchdog timer reset • Firmware reset • SPI2 reset • SDIO reset A power-on reset signal is generated when the core supply voltage is applied. The reset signal remains active for 4 ms after the 1.8 V supply is stable. The signal is available on pin POR_N. The RST_N pin should be linked to the POR_N pin ...
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... NXP Semiconductors 10.2 Microcontroller subsystem Fig 5. Block diagram of the microcontroller subsystem The microcontroller subsystem is based around an ARM7TDMI-S RISC controller and has the following features: • Embedded nonvolatile memory: 256-kbit ROM • Embedded volatile memory: 5 • Instruction pre-fetch unit for enhanced microcontroller performance • ...
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AHB TRANSMIT DMA HW MAC TX interrupt HW MAC interrupt HW MAC RX interrupt RECEIVE DMA Fig 6. HW MAC block diagram MAC CRC 802.11b HEADER CALCULATION MODEM TX INSERTION AND INSERTION INTERFACE TRANSMIT CONTROL HW MAC CONTROL RECEIVE CONTROL ...
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... NXP Semiconductors The IEEE 802.11b compliant HW MAC supports the following features: • Data rates Mbit/s • SIFS timer • Cyclic Redundancy Check (CRC) calculation and checking • Back-off mechanism support • Automated transmit timing control • Automated TBTT/TXOP boundary checking • ...
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... NXP Semiconductors 10.4 WEP encryption and decryption coprocessor Fig 7. Block diagram of the WEP encryption and decryption coprocessor The WEP encryption and decryption coprocessor has the following features: • WEP 64-bit and 128-bit encryption and decryption • WEP2 support in conjunction with firmware running on the microcontroller • ...
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... NXP Semiconductors 10.6 General-purpose DMA engine Fig 9. Block diagram of the general-purpose DMA engine The general-purpose DMA engine can be used to move data from one memory location to another with minimum firmware involvement. Uses of the block include fragmentation and defragmentation assistance. 10.7 Physical layer transmitter ...
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... NXP Semiconductors The test modes available with the PHYTX block and their uses are given in Table 5. Test mode RANDOM 0101 CW 10.8 Physical layer receiver block control signals RX data DEMODULATOR RX control signals Fig 11. Block diagram of the physical layer receiver The PHYRX block is IEEE 802.11b compliant and supports the following features: • ...
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... NXP Semiconductors The operation performed by the demodulator is dependent on the data rate. For 1 Mbit Mbit/s rates the demodulator will differentially decode the output of a Barker de-spreader. For 5.5 Mbit Mbit/s data rates a CCK decoder is used to translate the output of the equalizer into data bits. In both cases, a descrambler removes the pseudorandom sequence from the data ...
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... NXP Semiconductors 10.10 System timers Fig 13. Block diagram of system timers The SA2443A contains five general-purpose timers and a WatchDog Timer (WDT). Table 6 Table 6. Timer name TIMER0 TIMER1 TIMER2 TIMER3 TIMER4 WDT Timers and 4 can be programmed with a start value. Operation can be either single shot or continuous ...
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... NXP Semiconductors 10.11 Interrupt control unit interrupts input Fig 14. Block diagram of the IRQ/FIQ interrupt controller Two primary interrupt controllers are implemented: • Fast Interrupt reQuest (FIQ) interrupt controller • Interrupt ReQuest (IRQ) interrupt controller For each of the primary interrupt controllers there is a secondary GPIO interrupt controller ...
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... NXP Semiconductors 10.12 Universal asynchronous receiver transmitter Fig 15. Block diagram of the UART interface The Universal Asynchronous Receiver Transmitter (UART) supports the following features: • Parity generation and detection: even, odd, fixed logic 1 or logic parity • Stop bit generation: 1, 1.5 (5-bit character size only stop bits • ...
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... NXP Semiconductors 10.13 Master/slave serial peripheral interface Fig 16. Block diagram of the master/slave SPI interface (SPI1) The master/slave SPI interface (SPI1) has the following features: • Master or slave mode operation • SPI mode 0 and mode 3 supported in both master and slave modes • ...
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... NXP Semiconductors 10.14 High-speed slave serial peripheral interface SPI_EXT_INT SPI_SS_N SPI_MOSI SPI_MISO Fig 17. Block diagram of the high-speed SPI slave interface (SPI2) The high-speed SPI slave interface (SPI2) has the following features: • SPI mode 3 slave interface • Mbit/s data transfer rate (when SPI_MOSI is clocked from the positive edge of SPI_SCK) • ...
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... NXP Semiconductors 10.14.1 SPI interface The SPI interface operates entirely in the SPI clock domain. This enables the use of a higher SPI clock frequency than would be allowed with the usual oversampling scheme. SPI2 clock frequencies MHz are allowed. The SPI_SCK for SPI2 only needs to run when a data transfer is in progress. No additional clock pulses are needed ...
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... NXP Semiconductors The host mailboxes are written to by the SA2443A microcontroller and read from by the host. A host interrupt is signaled on the SPI_EXT_INT pin when the microcontroller writes to one of the host mailboxes. Eight scratch registers are provided: 4 local registers (SPI2_LOC_SR0 to SPI2_LOC_SR3; see see ...
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... NXP Semiconductors 10.14.4.3 Host-to-slave DMA transfer The host-to-slave DMA command sequence is used to transfer data from the host into internal memory in the SA2443A and consists of the following packets: • DMA initialization packet (16-bit, host-to-slave); see • DMA length packet (16-bit, host-to-slave); see • ...
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... NXP Semiconductors 10.14.5 SPI2 registers 10.14.5.1 Register overview Table 16. SPI2 registers Register Address Access SPI2_LOC_ISCR 00h SPI2_HST_ISCR 01h SPI2_DMA_SCR 02h SPI2_LOC_MB0 05h SPI2_LOC_MB1 06h SPI2_LOC_MB2 07h SPI2_LOC_MB3 08h SPI2_LOC_SR0 0Ah SPI2_LOC_SR1 0Bh SPI2_LOC_SR2 0Ch SPI2_LOC_SR3 0Dh SPI2_HST_MB0 0Fh SPI2_HST_MB1 10h SPI2_HST_MB2 ...
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... NXP Semiconductors Table 17. SPI2_LOC_ISCR register - SPI2 local mailbox interrupt status and control (00h) Legend: * reset value Bit Symbol 4 LMB0_INT_EN 3 LMB3_INT_STAT 2 LMB2_INT_STAT 1 LMB1_INT_STAT 0 LMB0_INT_STAT [1] This bit will be cleared following a local read. Table 18. SPI2_HST_ISCR register - SPI2 host mailbox interrupt status and control (01h) ...
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... NXP Semiconductors Table 18. SPI2_HST_ISCR register - SPI2 host mailbox interrupt status and control (01h) Legend: * reset value Bit Symbol 1 HMB1_INT_STAT 0 HMB0_INT_STAT [1] This bit will be cleared following a host read. Table 19. SPI2_DMA_SCR register - SPI2 DMA status and control (02h) Legend: * reset value Bit Symbol ...
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... NXP Semiconductors [1] Table 20. SPI2_LOC_MBn register - SPI2 local mailbox n (05h to 08h) Legend: * reset value Bit Symbol MBOX_DATA[7:0] [1] Register definition is the same for all local mailboxes; replace n with the mailbox number (0 to 3). [2] Writing to this register generates an interrupt to the local microcontroller if bit LMBn_INT_EN is set in register SPI2_LOC_ISCR (see Table 17) ...
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... NXP Semiconductors Table 24. SPI2_RST_CR register - SPI2 reset control (19h) Legend: * reset value Bit Symbol 0 RST_SA2443A [1] A host write to this bit will result in the SA2443A being reset. Table 25. SPI2_DMA_ISCR register - SPI2 DMA interrupt status and control (1Ah) Legend: * reset value Bit Symbol ...
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... NXP Semiconductors 10.15 Secure digital interface SD_CLK SD_CMD SD_DAT3 SD_DAT2 SD_DAT1 SD_DAT0 Fig 19. Block diagram of the secure digital interface The secure digital interface has the following features: • Compliant with version 1.00 of the SDIO standard • Supports SPI, SD1 and SD4 modes • ...
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... NXP Semiconductors 10.15.1 Mailboxes and scratch registers The SDIO interface contains 8 mailboxes: 4 local mailboxes (SD_LOC_MB0 to SD_LOC_MB3; see see Table The local mailboxes are written by the host and read by the SA2443A microcontroller. A local SDIO interrupt is generated when the host writes to one of the local mailboxes. ...
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... NXP Semiconductors 10.15.4 SDIO registers 10.15.4.1 Register overview Table 26. SDIO registers Registers Address Card common control registers SD_CCCR_REV 0 0000h SD_SD_REV 0 0001h SD_IOE 0 0002h SD_IOR 0 0003h SD_IEN 0 0004h SD_INT 0 0005h SD_AS_RES 0 0006h SD_BUS_CR 0 0007h SD_CAPABILITY 0 0008h SD_CCIS_PTR 0 0009h SD_BUS_STAT 0 000Ch SD_FS 0 000Dh ...
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... NXP Semiconductors Table 26. SDIO registers …continued Registers Address SD_LOC_SR0 0 0128h SD_LOC_SR1 0 012Ch SD_LOC_SR2 0 0130h SD_LOC_SR3 0 0134h SD_HST_MB0 0 013Ch SD_HST_MB1 0 0140h SD_HST_MB2 0 0144h SD_HST_MB3 0 0148h SD_HST_SR0 0 0150h SD_HST_SR1 0 0154h SD_HST_SR2 0 0158h SD_HST_SR3 0 015Ch SD_RST_CR 0 0164h SD_DMA_ISCR 0 0168h SD_H2F_DSIZEL 0 0198h SD_H2F_DSIZEH 0 019Ch SD_F2H_DSIZEL ...
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... NXP Semiconductors Table 29. SD_IOE register - SDIO I/O enable (FN0 0 0002h) Legend: * reset value Bit Symbol IOE1 0 - Table 30. SD_IOR register - SDIO I/O ready (FN0 0 0003h) Legend: * reset value Bit Symbol IOR1 0 - Table 31. SD_IEN register - SDIO interrupt enable (FN0 0 0004h) Legend: * reset value ...
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... NXP Semiconductors Table 33. SD_AS_RES register - SDIO I/O abort select and reset (FN0 0 0006h) Legend: * reset value Bit Symbol RES AS[2:0] Table 34. SD_BUS_CR register - SDIO bus interface control (FN0 0 0007h) Legend: * reset value Bit Symbol 7 CD_DISABLE 6 SCSI 5 ECSI and 0 BUS_WIDTH[1:0] Table 35. ...
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... NXP Semiconductors Table 35. SD_CAPABILITY register - SDIO card capability (FN0 0 0008h) Legend: * reset value Bit Symbol 5 E4MI 4 S4MI 3 SBS 2 SRW 1 SMB 0 SDC Table 36. SD_CCIS_PTR register - SDIO common CIS pointer (FN0 0 0009h) Legend: * reset value Bit Symbol CCIS_PTR[23:0] Table 37. SD_BUS_STAT register - SDIO bus status (FN0 0 000Ch) ...
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... NXP Semiconductors Table 37. SD_BUS_STAT register - SDIO bus status (FN0 0 000Ch) Legend: * reset value Bit Symbol 0 BS Table 38. SD_FS register - SDIO function select (FN0 0 000Dh) Legend: * reset value Bit Symbol FS[3:0] Table 39. SD_EX register - SDIO execution flags (FN0 0 000Eh) Legend: * reset value ...
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... NXP Semiconductors Table 41. SD_BLK_SIZE0 - SDIO function 0 block size (FN0 0 0010h) Legend: * reset value Bit Symbol BLK_SIZE[15:0] 10.15.4.3 Function basic registers The function basic registers are located in the function 0 address space. Table 42. SD_FIC_STD1 register - SDIO function 1 standard function interface code (FN0 0 0100h) ...
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... NXP Semiconductors Table 47. SD_BLK_SIZE1 register - SDIO function 1 I/O block size (FN0 0 0110h) Legend: * reset value Bit Symbol BLK_SIZE[15:0] 10.15.4.4 Function 1 registers Function 1 registers are located in the function 1 address space. Table 48. SD_LOC_ISCR register - SDIO local mailbox interrupt status and control (FN1 0 0100h) ...
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... NXP Semiconductors Table 49. SD_HST_ISCR register - SDIO host mailbox interrupt status and control (FN1 0 0104h) Legend: * reset value Bit Symbol 7 HMB3_INT_EN 6 HMB2_INT_EN 5 HMB1_INT_EN 4 HMB0_INT_EN 3 HMB3_INT_STAT 2 HMB2_INT_STAT 1 HMB1_INT_STAT 0 HMB0_INT_STAT [1] This bit will be cleared following a host read. Table 50. SD_DMA_SCR register - SDIO DMA status and control (FN1 0 0108h) ...
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... NXP Semiconductors Table 50. SD_DMA_SCR register - SDIO DMA status and control (FN1 0 0108h) Legend: * reset value Bit Symbol 4 H2F_DMA0_STAT 3 F2H_DMA_PEND1 2 F2H_DMA_PEND0 1 NEXT_F2H_CHAN 0 NEXT_H2F_CHAN Table 51. SD_H2F_DDAW register - SDIO host-to-function DMA data access window (FN1 0 010Ch) Legend: * reset value Bit Symbol DMA_DAW[7:0] Table 52. ...
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... NXP Semiconductors [1] Table 54. SD_LOC_SRn register - SDIO local scratch register n (FN1 0 0128h to 0 0134h) Legend: * reset value Bit Symbol SCRCH_DATA[7:0] [1] Register definition is the same for all local scratch registers; replace n with the scratch register number (0 to 3). [1] Table 55. SD_HST_MBn register - SDIO host mailbox n (FN1 0 013Ch to 0 0148h) ...
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... NXP Semiconductors Table 58. SD_DMA_ISCR register - SDIO DMA interrupt status and control (FN1 0 0168h) Legend: * reset value Bit Symbol 7 H2F1_INT_EN 6 H2F0_INT_EN 5 F2H1_INT_EN 4 F2H0_INT_EN 3 H2F1_INT_STAT 2 H2F0_INT_STAT 1 F2H1_INT_STAT 0 F2H0_INT_STAT [1] This bit will be cleared by a local read. Table 59. SD_H2F_DSIZEL register - SDIO host-to-function DMA data size - lower byte (FN1 0 0198h) ...
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... NXP Semiconductors Table 61. SD_F2H_DSIZEL register - SDIO function-to-host DMA data size - lower byte (FN1 0 01A0h) Legend: * reset value Bit Symbol DATA_SIZE[7:0] Table 62. SD_F2H_DSIZEH register - SDIO function-to-host DMA data size - upper byte (FN1 0 01A4h) Legend: * reset value Bit Symbol DATA_SIZE[15:8] Table 63. SD_F2H_DMAERR register - SDIO function-to-host DMA error (FN1 0 01A8h) ...
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... NXP Semiconductors 11. Limiting values Table 65. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V VCO analog supply voltage DDA(VCO) V analog supply voltage DDA V I/O digital supply voltage DDD(IO) V core digital supply voltage DDD(C) V power amplifier supply voltage ...
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... NXP Semiconductors 13. Static characteristics Table 67. Supply characteristics All values at nominal supply voltage; T Symbol Parameter Core logic supply V core digital supply voltage DDD(C) I sleep core supply current DD(C)(sleep) I receive core supply current DD(C)(rcv) I transmit core supply current DD(C)(tx) Digital I/O, analog RF and VCO supplies ...
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... NXP Semiconductors 93.9 I DD(C)(rcv) (mA) 93.7 93 Fig 20. Core supply current in receive mode as a function of temperature 102 I DDA(tx) (mA) 98 (1) ( Fig 22. Digital I/O, analog RF and VCO supply current in transmit mode for 11 Mbit/s at fixed gain setting CFh as a function of temperature ...
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... NXP Semiconductors 14. Dynamic characteristics 14.1 Receiver Table 69. Receiver characteristics All values at nominal supply voltage; T Symbol Parameter Receiver sensitivity; see Figure 24 S receiver sensitivity RX Maximum input level V maximum input voltage i(max) Adjacent channel rejection ACR adjacent channel rejection Receiver tolerances t delay time variation ...
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... NXP Semiconductors (dBm Mbit/s packets in channel (dBm Mbit/s packets in channel Fig 24. Receiver sensitivity as a function of temperature BGW200EG_1 Product data sheet 001aad209 (dBm) 89 (1) ( 110 amb b. 1 Mbit/s packets in channel 14 001aad211 (dBm) 81 (3) ( 110 amb d. 11 Mbit/s packets in channel 14 Rev. 01 — ...
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... NXP Semiconductors 14.2 Transmitter Table 70. Transmitter characteristics All values at nominal supply voltage; T Symbol Parameter Linear output power; see Figure 25 P output power o Transmit spectrum mask; see Figure 27 ACPR adjacent channel power ratio ACPR alternate adjacent alt channel power ratio Transmit modulation accuracy ...
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... NXP Semiconductors (dBm Mbit/s modulation in channel Fig 25. Output power at gain setting CFh as a function of temperature (dBm Mbit/s modulation in channel Fig 26. Output power at gain setting AFh as a function of temperature BGW200EG_1 Product data sheet 001aad213 (dBm (1) (2) ( 110 amb b ...
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... NXP Semiconductors 30 ACPR (dBr) 31 (2) ( Mbit/s modulation in channel Fig 27. Adjacent channel power ratio at gain setting CFh as a function of temperature 49 ACPR alt (dBr (3) (2) ( Mbit/s modulation in channel Fig 28. Alternate adjacent channel power ratio at gain setting CFh as a function of temperature ...
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... NXP Semiconductors 14.3 Clock and reset Table 71. Dynamic characteristics for clock and reset signals Symbol Parameter Reference clock; see Figure 29 f reference clock frequency clk(ref) t reference clock HIGH pulse width wH(clk)(ref) t reference clock LOW pulse width wL(clk)(ref) Sleep clock; see ...
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... NXP Semiconductors Fig 32. Power-on reset timing 14.4 SPI1 interface Table 72. Dynamic characteristics for SPI1 Symbol Parameter SPI clock input; see Figure 33 T SPI_SCK period SPI_SCK t clock HIGH time clk(H) t clock LOW time clk(L) SPI slave select input; see Figure 35 t SPI_SS_N set-up time ...
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... NXP Semiconductors SPI_SCK (CPOL = 0) SPI_SCK (CPOL = 1) SPI_SS_N SPI_MOSI (output) SPI_MISO (input) Fig 33. SPI1 master timing (CPHA = 0) SPI_SCK (CPOL = 0) SPI_SCK (CPOL = 1) SPI_SS_N SPI_MOSI (output) SPI_MISO (input) Fig 34. SPI1 master timing (CPHA = 1) BGW200EG_1 Product data sheet T SPI_SCK t d(o)(SPI_MOSI) t su(SPI_MISO) T SPI_SCK t d(o)(SPI_MOSI) ...
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... NXP Semiconductors SPI_SCK (CPOL = 0) SPI_SCK (CPOL = 1) SPI_SS_N SPI_MOSI (input) SPI_MISO (output) Fig 35. SPI1 slave timing (CPHA = 0) SPI_SCK (CPOL = 0) SPI_SCK (CPOL = 1) SPI_SS_N SPI_MOSI (input) SPI_MISO (output) Fig 36. SPI1 slave timing (CPHA = 1) BGW200EG_1 Product data sheet T SPI_SCK t su(SPI_SS_N) t su(SPI_MOSI en(o)(SPI_MISO) d(o)(SPI_MISO) ...
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... NXP Semiconductors 14.5 SPI2 interface Table 73. Dynamic characteristics for SPI2 Symbol Parameter SPI clock input; see Figure 37 and T SPI_SCK period SPI_SCK t clock HIGH time clk(H) t clock LOW time clk(L) SPI slave select input; see Figure 37 t SPI_SS_N set-up time su(SPI_SS_N) t SPI_SS_N hold time h(SPI_SS_N) SPI_MOSI input ...
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... NXP Semiconductors SPI_SCK SPI_SS_N SPI_MOSI (input) SPI_MISO (output) Fig 38. SPI2 timing (SPI_MISO clocked on positive edge of SPI_SCK) 14.6 SDIO interface Table 74. Dynamic characteristics for the SDIO interface Symbol Parameter SD clock input; see Figure 39 T SD_CLK period SD_CLK t clock HIGH time clk(H) t clock LOW time clk(L) SD command input/output ...
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... NXP Semiconductors SD_CMD/DAT (output) SD_CMD/DAT (input) Fig 39. SDIO interface timing BGW200EG_1 Product data sheet T SD_CLK SD_CLK t d(o)(SD_CMD) t d(o)(SD_DATx) t su(i)(SD_CMD) t su(i)(SD_DATx) Rev. 01 — 18 July 2007 BGW200EG IEEE 802.11b System-in-Package t t clk(H) clk(L) t h(i)(SD_CMD) t h(i)(SD_DATx) © NXP B.V. 2007. All rights reserved. ...
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... NXP Semiconductors 15. Package outline HLLGA68: plastic thermal enhanced low profile land grid array package; 68 lands; body 1.3 mm land 1 index area land 1 68 index area DIMENSIONS (mm are the original dimensions) A UNIT max 0.32 10.1 8.1 1.4 mm 0.28 9.9 7.9 OUTLINE VERSION IEC SOT858-1 Fig 40 ...
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... NXP Semiconductors 16. Soldering 16.1 Printed-circuit board 16.1.1 PCB footprint layout 13.30 13.00 0.35 4.10 1.80 solder lands solder paste solder resist occupied area Reflow soldering footprint for SOT858-1; non solder mask defined; copper defined Fig 41. PCB footprint outline BGW200EG_1 Product data sheet 10 ...
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... NXP Semiconductors 16.1.1.1 Vias design Through-hole vias in the ground plane should be plugged and preferably have a top metallization. In case that through-hole vias are used to connect the terminal pads, than they should be placed outside the package area to prevent shorts and voids. Voiding in the solder joints can further be minimized by locating the through-hole vias under the stencil web area or close to the corner of the stencil apertures (see Microvias can be placed in both central ground pad and terminal pads ...
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... NXP Semiconductors 16.2 Soldering 16.2.1 Solder paste Standard (no-clean) Sn/Pb ( Pb-free solder pastes should be used for soldering the package. Solder pastes should be selected based on their printing and reflow behavior. For Pb-free solder paste it is recommended to use ‘SAC’ type solder paste (e.g. SnAg3.8Cu0.7) with melting point of 217 C. ...
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... NXP Semiconductors Table 75. Parameter Average ramp-up rate [T Preheat • Temperature min [T • Temperature max [T • Time t Time maintained above • Temperature (T • Time (t Maximum peak temperature (T Time within actual peak temperature (T Ramp-down rate Minimum peak temperature [T Time [1] Ramp-up and ramp-down is lower than specified in JEDEC J-STD-020C. ...
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... NXP Semiconductors 16.3.2 Site redress After the component is removed, the PCB solder land needs to be cleaned properly best to use a combination of a blade-style conductive tool and desoldering braid. The width of the blade should be matched to the maximum width of the footprint and the blade temperature should be low enough not to cause any damage to the circuit board ...
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... NXP Semiconductors 19. Abbreviations Table 76. Acronym ACK ADC AES AGC AHB ATIM BGA BT CBC-MAC CCA CCCR CCK CCM CDM CIS CRC CSA CTS DCS DMA DSSS EDCF EEPROM EMI ESD EVM FCC FIQ FIRDAC GPIO GSM HASL HBM HCF HCI HW IBSS ICU ...
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... NXP Semiconductors Table 76. Acronym IPU IRQ ISI ISM LNA LSB MAC MIC MIPS MSB MSL NAV NIC OSP PCB PDA PER PHY PHYRX PHYTX PLCP PSDU PTA QoS QPSK RFIF RISC RoHS ROM RSSI RTS RX SCU SDIO SDRAM SIFS SPI TBTT ...
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... NXP Semiconductors Table 76. Acronym TXOP UART VCO VoIP VPB WDT WEP WinCE WLAN WMM WPA 20. Revision history Table 77. Revision history Document ID Release date BGW200EG_1 20070718 BGW200EG_1 Product data sheet Abbreviations …continued Description Transmission Opportunity Universal Asynchronous Receiver Transmitter Voltage-Controlled Oscillator Voice over Internet Protocol ...
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... For detailed and full information see the relevant full data sheet, which is available on request via the local NXP Semiconductors sales office. In case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail ...
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... NXP Semiconductors 23. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.1 General . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 2.2 Power management . . . . . . . . . . . . . . . . . . . . . 1 2.3 Radio transceiver . . . . . . . . . . . . . . . . . . . . . . . 2 2.4 Baseband hardware . . . . . . . . . . . . . . . . . . . . . 2 2.5 Software . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2.6 Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 4 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 5 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 6 7 Functional description . . . . . . . . . . . . . . . . . . . 9 7 ...
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... NXP Semiconductors 21.4 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 22 Contact information Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 BGW200EG IEEE 802.11b System-in-Package Please be aware that important notices concerning this document and the product(s) described herein, have been included in section ‘Legal information’. © NXP B.V. 2007. For more information, please visit: http://www.nxp.com For sales office addresses, please send an email to: salesaddresses@nxp ...