BGW200EG/01,518 NXP Semiconductors, BGW200EG/01,518 Datasheet - Page 67

• Manufacturer Part Number: BGW200EG/01,518
• Description: IC WLAN SIP MOD 802.11B 68HVQFN
• Manufacturer: NXP Semiconductors
• Series: BGW200r

Specifications of BGW200EG/01,518

• Frequency: 2.4GHz ~ 2.5GHz
• Modulation Or Protocol: DBPSK, DQPSK, CCK
• Applications: PDA's, Portable Audio/Video, Smartphones
• Power - Output: 8dBm ~ 18dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Package / Case: 68-VQFN Exposed Pad, 68-HVQFN, 68-SQFN, 68-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Operating Temperature: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Other names: 935279198518; BGW200EG/01-T; BGW200EG/01-T

NXP Semiconductors
BGW200EG_1
Product data sheet
16.1.1.1 Vias design
16.1.2 PCB finish
16.1.3 Stencil design
Through-hole vias in the ground plane should be plugged and preferably have a top
metallization. In case that through-hole vias are used to connect the terminal pads, than
they should be placed outside the package area to prevent shorts and voids.
Voiding in the solder joints can further be minimized by locating the through-hole vias
under the stencil web area or close to the corner of the stencil apertures (see
Microvias can be placed in both central ground pad and terminal pads. Voiding in the
solder joints can further be minimized by locating the microvias under the stencil web area
or close to the corner of the stencil apertures.
The packages can be used on a variety of PCB finishes such as immersion gold (Ni/Au) or
Hot Air Solder Level (HASL) or Organic Surface Protection (OSP).
Ni/Au finish is recommended. OSP is not recommended in cases that OSP does not
withstand a Pb-free or a double-sided reflow application.
The stencil opening for terminal pads should be 100 % of solder land size while the stencil
openings of the center/ground pad should be divided in an array, such that 80 % to 90 %
coverage of the center solder land is achieved. This array of openings minimizes the risk
of smearing during stencil print and risk of short circuit or voiding during reflow. Stencil
thickness can range from 0.10 mm to 0.15 mm. Using rounded corners, tapered and
smoothed walls can further optimize solder paste transfer.
Fig 42. Via placing around solder land
Rev. 01 — 18 July 2007
IEEE 802.11b System-in-Package
001aad233
BGW200EG
© NXP B.V. 2007. All rights reserved.
Figure
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