BGW200EG/01,518 NXP Semiconductors, BGW200EG/01,518 Datasheet - Page 36

• Manufacturer Part Number: BGW200EG/01,518
• Description: IC WLAN SIP MOD 802.11B 68HVQFN
• Manufacturer: NXP Semiconductors
• Series: BGW200r

Specifications of BGW200EG/01,518

• Frequency: 2.4GHz ~ 2.5GHz
• Modulation Or Protocol: DBPSK, DQPSK, CCK
• Applications: PDA's, Portable Audio/Video, Smartphones
• Power - Output: 8dBm ~ 18dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Package / Case: 68-VQFN Exposed Pad, 68-HVQFN, 68-SQFN, 68-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Operating Temperature: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Other names: 935279198518; BGW200EG/01-T; BGW200EG/01-T

NXP Semiconductors
BGW200EG_1
Product data sheet
10.15.3.1 SDIO interface register access
10.15.3.2 Host-to-function 1 DMA transfer
10.15.3.3 Function 1-to-host DMA transfer
10.15.1 Mailboxes and scratch registers
10.15.2 DMA controller
10.15.3 SDIO host operations
The SDIO interface contains 8 mailboxes: 4 local mailboxes (SD_LOC_MB0 to
SD_LOC_MB3; see
see
The local mailboxes are written by the host and read by the SA2443A microcontroller.
A local SDIO interrupt is generated when the host writes to one of the local mailboxes.
The enabling of generation of the interrupt is programmable.
The host mailboxes are written by the SA2443A microcontroller and read by the host.
A host interrupt is signaled when the microcontroller writes to one of the host mailboxes.
Eight scratch registers are provided: 4 local (SD_LOC_SR0 to SD_LOC_SR3; see
Table
registers are accessed in the same way as the mailbox registers, the only difference
being, that no interrupts are generated when the scratch registers are written to.
The DMA controller provides efficient data transfer of data between the host and
SA2443A internal memory. The host initiates all DMA transfers.
The DMA controller supports data transfers from 0 bytes to 65535 bytes.
The host can read from and write to registers in the SA2443A SDIO interface and initiate
DMA transfers.
Host-addressable registers within the SA2443A SDIO interface can be accessed with the
SDIO IO_RW_DIRECT command (CMD52). In the case of a read, the register value will
be returned using the IO_RW_DIRECT response (R5).
To initiate a host-to-function DMA transfer the host must first program the transfer size (in
bytes) into the SD_H2F_DSIZEL and SD_H2F_DSIZEH registers (see
Table
size value). The data can then be transferred using an IO_RW_EXTENDED command
(CMD53) write to the SD_H2F_DDAW register; see
of CMD53 should be set to logic 1, indicating a block mode transfer and the OP code bit
should be set to logic 0, indicating a multibyte R/W to fixed address.
For a function-to-host DMA transfer the host must read the transfer size (in bytes) from the
SD_F2H_DSIZEL and SD_F2H_DSIZEH registers (see
IO_RW_DIRECT command (two accesses are required to read the 16-bit size value). The
data can then be transferred using an IO_RW_EXTENDED command (CMD53) read from
the SD_F2H_DDAW register; see
be set to logic 1, indicating a block mode transfer and the OP code bit should be set to
logic 0, indicating a multibyte R/W to fixed address.
Table
54) and 4 host (SD_HST_SR0 to SD_HST_SR3; see
60) using the IO_RW_DIRECT command (two writes are required to set the 16-bit
55).
Table
Rev. 01 — 18 July 2007
53) and 4 host mailboxes (SD_HST_MB0 to SD_HST_MB3;
Table
52. Note that the block mode bit of CMD53 should
Table
IEEE 802.11b System-in-Package
Table 61
51. Note that the block mode bit
Table
BGW200EG
and
56). The scratch
Table
© NXP B.V. 2007. All rights reserved.
Table 59
62) using the
and
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