BGW200EG/01,518 NXP Semiconductors, BGW200EG/01,518 Datasheet - Page 28

• Manufacturer Part Number: BGW200EG/01,518
• Description: IC WLAN SIP MOD 802.11B 68HVQFN
• Manufacturer: NXP Semiconductors
• Series: BGW200r

Specifications of BGW200EG/01,518

• Frequency: 2.4GHz ~ 2.5GHz
• Modulation Or Protocol: DBPSK, DQPSK, CCK
• Applications: PDA's, Portable Audio/Video, Smartphones
• Power - Output: 8dBm ~ 18dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Package / Case: 68-VQFN Exposed Pad, 68-HVQFN, 68-SQFN, 68-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Operating Temperature: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Other names: 935279198518; BGW200EG/01-T; BGW200EG/01-T

NXP Semiconductors
BGW200EG_1
Product data sheet
10.14.4.1 Write register command
10.14.4.2 Read register command
10.14.3 DMA controller
10.14.4 Host SPI operations
The host mailboxes are written to by the SA2443A microcontroller and read from by the
host. A host interrupt is signaled on the SPI_EXT_INT pin when the microcontroller writes
to one of the host mailboxes.
Eight scratch registers are provided: 4 local registers (SPI2_LOC_SR0 to
SPI2_LOC_SR3; see
see
registers, the only difference being that no interrupts are generated when the scratch
registers are written.
The DMA controller provides efficient transfer of data between the host and SA2443A
internal memory. The host initiates all DMA transfers.
The DMA controller supports data transfers from 0 bytes to 65535 bytes.
The host can read or write registers in the SPI2 interface and initiate DMA transfers.
The write register command is used by the host to write data into SPI interface registers.
It consists of one 16-bit packet. The command format is shown in
Table 7.
The read register command sequence is used by the host to read data from SPI interface
registers and consists of two packets:
Table 8.
Table 9.
Bit
15
14 to 10
9 and 8
7 to 0
Bit
15
14 to 10
9 to 0
Bit
15 to 8
7 to 0
•
•
Read register initialization packet (16-bit, host-to-slave). The format of this packet is
shown in
Read data package (16-bit, slave-to-host). The format of this packet is shown in
Table
Table
9.
23). The scratch registers are accessed in the same way as the mailbox
Symbol
COMMAND_TYPE
REG_ADDR[4:0]
-
REG_DATA[7:0]
Symbol
COMMAND_TYPE
REG_ADDR[4:0]
-
Symbol
-
REG_DATA[7:0]
Write register command packet
Read register command initialization packet
Read register command data packet
Table
8.
Table
Rev. 01 — 18 July 2007
21) and 4 host registers (SPI2_HST_SR0 to SPI2_HST_SR3;
Value
1h
00h to 1Ah
-
00h to FFh
Value
0h
00h to 1Ah
-
Value
-
00h to FFh
Description
indicates a host-to-slave transfer
see
reserved
register data
Description
reserved
register data
Description
indicates a slave-to-host transfer
see
reserved
Table 16
Table 16
IEEE 802.11b System-in-Package
for valid register addresses
for valid register addresses
BGW200EG
Table
© NXP B.V. 2007. All rights reserved.
7.
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