BGW200EG/01,518 NXP Semiconductors, BGW200EG/01,518 Datasheet - Page 35

• Manufacturer Part Number: BGW200EG/01,518
• Description: IC WLAN SIP MOD 802.11B 68HVQFN
• Manufacturer: NXP Semiconductors
• Series: BGW200r

Specifications of BGW200EG/01,518

• Frequency: 2.4GHz ~ 2.5GHz
• Modulation Or Protocol: DBPSK, DQPSK, CCK
• Applications: PDA's, Portable Audio/Video, Smartphones
• Power - Output: 8dBm ~ 18dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Package / Case: 68-VQFN Exposed Pad, 68-HVQFN, 68-SQFN, 68-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Operating Temperature: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Other names: 935279198518; BGW200EG/01-T; BGW200EG/01-T

NXP Semiconductors
BGW200EG_1
Product data sheet
10.15 Secure digital interface
The secure digital interface has the following features:
The SDIO interface of the SA2443A is intended for high-throughput host communication.
The SDIO clock is independent of the bus clock (no over-sampling) and has a maximum
operating frequency of 25 MHz.
Most operations are handled by the SDIO block hardware. The role of the SA2443A
firmware is to handle interrupts and to specify the location of the DMA data in SA2443A
memory.
Fig 19. Block diagram of the secure digital interface
•
•
•
•
•
•
•
•
Compliant with version 1.00 of the SDIO standard
Supports SPI, SD1 and SD4 modes
SA2443A mapped to SDIO function 1
Block sizes up to 2048 bytes supported
DMA controller
8 mailboxes (4 local and 4 host)
8 scratch registers (4 local and 4 host)
SDIO master can reset the SA2443A
SD_DAT3
SD_DAT2
SD_DAT1
SD_DAT0
SD_CMD
SD_CLK
INTERFACE
Rev. 01 — 18 July 2007
SDIO
SDIO CLOCK
SCRATCH REGISTER 0-3
SCRATCH REGISTER 0-3
LOCAL MAILBOX 0-3
DMA CONTROLLER
HOST MAILBOX 0-3
SDIO INTERRUPT
SDIO STATUS
REGISTERS
CONTROL
LOCAL
HOST
BUS CLOCK
IEEE 802.11b System-in-Package
001aad204
BGW200EG
VPB
SDIO interrupt
SDIO SW interrupt
SDIO DMA interrupt
SDIO reset
© NXP B.V. 2007. All rights reserved.
AHB
35 of 76