BGW200EG/01,518 NXP Semiconductors, BGW200EG/01,518 Datasheet - Page 30

• Manufacturer Part Number: BGW200EG/01,518
• Description: IC WLAN SIP MOD 802.11B 68HVQFN
• Manufacturer: NXP Semiconductors
• Series: BGW200r

Specifications of BGW200EG/01,518

• Frequency: 2.4GHz ~ 2.5GHz
• Modulation Or Protocol: DBPSK, DQPSK, CCK
• Applications: PDA's, Portable Audio/Video, Smartphones
• Power - Output: 8dBm ~ 18dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Package / Case: 68-VQFN Exposed Pad, 68-HVQFN, 68-SQFN, 68-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Operating Temperature: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Other names: 935279198518; BGW200EG/01-T; BGW200EG/01-T

NXP Semiconductors
Table 16.
Table 17.
Legend: * reset value
BGW200EG_1
Product data sheet
Register
SPI2_LOC_ISCR
SPI2_HST_ISCR
SPI2_DMA_SCR
SPI2_LOC_MB0
SPI2_LOC_MB1
SPI2_LOC_MB2
SPI2_LOC_MB3
SPI2_LOC_SR0
SPI2_LOC_SR1
SPI2_LOC_SR2
SPI2_LOC_SR3
SPI2_HST_MB0
SPI2_HST_MB1
SPI2_HST_MB2
SPI2_HST_MB3
SPI2_HST_SR0
SPI2_HST_SR1
SPI2_HST_SR2
SPI2_HST_SR3
SPI2_RST_CR
SPI2_DMA_ISCR
Bit
7
6
5
Symbol
LMB3_INT_EN
LMB2_INT_EN
LMB1_INT_EN
SPI2 registers
SPI2_LOC_ISCR register - SPI2 local mailbox interrupt status and control (00h)
10.14.5.1 Register overview
10.14.5.2 Register details
10.14.5 SPI2 registers
Address Access
00h
01h
02h
05h
06h
07h
08h
0Ah
0Bh
0Ch
0Dh
0Fh
10h
11h
12h
14h
15h
16h
17h
19h
1Ah
Local
R/W
R
R/W
R
R
R
R
R
R
R
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Access
Local
R/W
R/W
R/W
Host
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R
R
R
R
R
R
R
R
R/W
R
Host
R
R
R
Rev. 01 — 18 July 2007
Value
0*
1
0*
1
0*
1
Description
local mailbox interrupt status and control
host mailbox interrupt status and control
DMA status and control register
local mailbox 0 (host-to-slave)
local mailbox 1 (host-to-slave)
local mailbox 2 (host-to-slave)
local mailbox 3 (host-to-slave)
local scratch register 0 (host-to-slave)
local scratch register 1 (host-to-slave)
local scratch register 2 (host-to-slave)
local scratch register 3 (host-to-slave)
host mailbox 0 (slave-to-host)
host mailbox 1 (slave-to-host)
host mailbox 2 (slave-to-host)
host mailbox 3 (slave-to-host)
host scratch register 0 (slave-to-host)
host scratch register 1 (slave-to-host)
host scratch register 2 (slave-to-host)
host scratch register 3 (slave-to-host)
reset control register
DMA interrupt status and control
Description
local mailbox 3 interrupt control
do not generate interrupt when mailbox is written
generate interrupt when mailbox is written by the host
local mailbox 2 interrupt control
do not generate interrupt when mailbox is written
generate interrupt when mailbox is written by the host
local mailbox 1 interrupt control
do not generate interrupt when mailbox is written
generate interrupt when mailbox is written by the host
IEEE 802.11b System-in-Package
BGW200EG
© NXP B.V. 2007. All rights reserved.
Reference
Table 17
Table 18
Table 19
Table 20
Table 21
Table 22
Table 23
Table 24
Table 25
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