BGW200EG/01,518 NXP Semiconductors, BGW200EG/01,518 Datasheet - Page 10

• Manufacturer Part Number: BGW200EG/01,518
• Description: IC WLAN SIP MOD 802.11B 68HVQFN
• Manufacturer: NXP Semiconductors
• Series: BGW200r

Specifications of BGW200EG/01,518

• Frequency: 2.4GHz ~ 2.5GHz
• Modulation Or Protocol: DBPSK, DQPSK, CCK
• Applications: PDA's, Portable Audio/Video, Smartphones
• Power - Output: 8dBm ~ 18dBm
• Data Interface: PCB, Surface Mount
• Antenna Connector: PCB, Surface Mount
• Package / Case: 68-VQFN Exposed Pad, 68-HVQFN, 68-SQFN, 68-DHVQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Voltage - Supply: -
• Operating Temperature: -
• Sensitivity: -
• Memory Size: -
• Data Rate - Maximum: -
• Current - Transmitting: -
• Current - Receiving: -
• Other names: 935279198518; BGW200EG/01-T; BGW200EG/01-T

NXP Semiconductors
BGW200EG_1
Product data sheet
7.2 Subblock overview
will be the basis for smart phones and PDAs to communicate with a LAN network through
a WLAN access point both for voice (VoIP) and data access. It is designed to handle the
IEEE 802.11b specification.
The BGW200EG combines the IEEE 802.11b PHY and MAC with the embedded HCI
firmware for selected host operating systems through either the SPI or SDIO interfaces.
A typical example of the BGW200EG in its environment is illustrated in
with an antenna, reference clock and filtering as required by the application, this device
forms a complete WLAN solution. The system architecture is ideal for mobile products
and requires no load on the host processor. The host sleeps while the WLAN listens for
the beacon and is woken by the WLAN when appropriate.
Table 3
to the section of the data sheet that describes these blocks.
Table 3.
Block name
SA2405 RF transceiver
FIRDAC
AGC state machine automatic gain control state machine
RSSI
SA2411 RF power amplifier
PA
SA2443A Baseband/MAC
SCU
Processor:
SRAM
ROM
Fig 3. Typical application of the BGW200EG
ARM7TDMI-S
IPU
JTAG
(1) Host is typically a mobile device such as a cell phone or PDA.
(2) Serial EEPROM/flash is optional.
gives an overview of some subblocks shown in
Subblock overview
Description
finite impulse response digital-to-analog converter
receive signal strength indicator
power amplifier
system configuration unit
fast RISC processor controlling other blocks via AHB and
VPB buses
instruction pre-fetch unit
joint test action group interface for ARM7 emulation
system RAM for use by firmware
read only program memory
EEPROM/
FLASH
HOST
SERIAL
Rev. 01 — 18 July 2007
(1)
(2)
SDIO/
SPI2
SPI1
BGW200EG
IEEE 802.11b System-in-Package
Figure 1
001aad188
and provides a reference
BGW200EG
Figure
© NXP B.V. 2007. All rights reserved.
Reference
Section 8
Section 9
Section 10.1
Section 10.2
3. Together
10 of 76