XRT75R12DIB-F Exar Corporation, XRT75R12DIB-F Datasheet - Page 111

• Manufacturer Part Number: XRT75R12DIB-F
• Description: Peripheral Drivers & Components (PCIs) 12 Channel 3.3V-5V temp -45 to 85C
• Manufacturer: Exar Corporation

Specifications of XRT75R12DIB-F

• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V to 5 V
• Package / Case: TBGA-420
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.3
The overall SONET network consists of numerous "Synchronization Islands". As a consequence, whenever a
SONET signal is being transmitted from one "Synchronization Island" to another; that SONET signal will
undergo a "clock domain" change as it traverses the network. This clock domain change will result in periodic
pointer-adjustments occurring within this SONET signal. Depending upon the direction of this "clock-domain"
shift that the SONET signal experiences, there will either be periodic "incrementing" pointer-adjustment events
or periodic "decrementing" pointer-adjustment events within this SONET signal.
Regardless of whether a given SONET signal is experiencing incrementing or decrementing pointer
adjustment events, each pointer adjustment event will result in an abrupt 8-bit shift in the position of the SPE
within the STS-1 data-stream. If this STS-1 signal is transporting an "asynchronously-mapped" DS3 signal;
then this 8-bit shift in the location of the SPE (within the STS-1 signal) will result in approximately 8UIpp of jitter
within the asynchronously-mapped DS3 signal, as it is de-mapped from SONET. In
the Category I Intrinsic Jitter Requirements (per Telcordia GR-253-CORE) for DS3 applications” on
page 108
253-CORE. However, for now we will simply state that this 8UIpp of intrinsic jitter far exceeds these "intrinsic
jitter" requirements.
In summary, pointer-adjustments events are a "fact of life" within the SONET/SDH network. Further, pointer-
adjustment events, within a SONET signal that is transporting an asynchronously-mapped DS3 signal, will
impose a significant impact on the Intrinsic Jitter and Wander within that DS3 signal as it is de-mapped from
SONET.
In most applications (in which the LIU will be used in a SONET De-Sync Application) the user will typically
interface the LIU to a Mapper Device in the manner as presented below in
In this application, the Mapper IC will have the responsibility of receiving an STS-N signal (from the SONET
Network) and performing all of the following operations on this STS-N signal.
F
8.4
8.3.4
IGURE
Byte-de-interleaving this incoming STS-N signal into N STS-1 signals
Terminating each of these STS-1 signals
Extracting (or de-mapping) the DS3 signal(s) from the SPEs within each of these terminated STS-1 signals.
54. I
Clock Gapping Jitter
we will discuss the "Category I Intrinsic Jitter Requirements (for DS3 Applications) per Telcordia GR-
Why are we talking about Pointer Adjustments?
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
LLUSTRATION OF THE
STS-N Signal
T
YPICAL
DS3 to STS-N
DS3 to STS-N
A
Demapper
Demapper
Mapper/
PPLICATIONS FOR THE
Mapper/
IC
IC
107
De-Mapped (Gapped)
DS3 Data and Clock
LIU
IN A
TPDATA_n input pin
SONET D
TCLK_n input
Figure
LIU
LIU
54.
“Section 8.5, A Review of
E
-S
YNC
A
XRT75R12D
PPLICATION