XRT75R12DIB-F Exar Corporation, XRT75R12DIB-F Datasheet - Page 74

Peripheral Drivers & Components (PCIs) 12 Channel 3.3V-5V temp -45 to 85C

XRT75R12DIB-F

Manufacturer Part Number
XRT75R12DIB-F
Description
Peripheral Drivers & Components (PCIs) 12 Channel 3.3V-5V temp -45 to 85C
Manufacturer
Exar Corporation
Datasheet

Specifications of XRT75R12DIB-F

Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V to 5 V
Package / Case
TBGA-420
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
S
B
OURCE
IT
B
7 - 4
N
IT
T
UMBER
3
2
ABLE
7
L
EVEL
31: XRT75R12D R
Change of LOL Con-
Change of FL Con-
dition Interrupt Sta-
dition Interrupt Sta-
B
I
NTERRUPT
IT
6
Reserved
Reserved
N
tus
tus
AME
S
B
TATUS
IT
5
EGISTER
R
T
RUR
RUR
YPE
EGISTER
B
MAP
IT
Change of FL (FIFO Limit Alarm) Condition Interrupt Status - Ch n:
This RESET-upon-READ bit-field indicates whether or not the Change of FL
Condition Interrupt (for Channel n) has occurred since the last read of this
register.
0 - Indicates that the Change of FL Condition Interrupt has NOT occurred
since the last read of this register.
1 - Indicates that the Change of FL Condition Interrupt has occurred since
the last read of this register.
N
Change of Receive LOL (Loss of Lock) Condition Interrupt Status - Ch
n:
This RESET-upon-READ bit-field indicates whether or not the Change of
Receive LOL Condition Interrupt (for Channel n) has occurred since the last
read of this register.
0 - Indicates that the Change of Receive LOL Condition Interrupt has NOT
occurred since the last read of this register.
1 - Indicates that the Change of Receive LOL Condition Interrupt has
occurred since the last read of this register.
N
4
OTE
OTE
- C
SHOWING
:
: The user can determine the current state of the Receive LOL Defect
Interrupt Status
HANNEL N
Change of FL
condition by reading out the contents of Bit 3 (FL Alarm Declared)
within the Alarm Status Register.(n)
condition by reading out the contents of Bit 2 (Receive LOL Defect
Declared) within the Alarm Status Register.(n)
The user can determine the current state of the FIFO Alarm
Condition
B
Ch_n
RUR
70
IT
I
NTERRUPT
3
A
DDRESS
Change of LOL
Interrupt Status
S
Condition
TATUS
L
Ch_n
B
RUR
OCATION
IT
D
ESCRIPTION
2
R
EGISTERS
= 0
Change of LOS
nterrupt Status
XM
Condition
Ch_n
B
RUR
2 (
IT
(ISR_
M
1
= 0-5 & 8-D)
N
)
(
N
Change of DMO
Interrupt Status
= [0:11])
Condition
Ch_n
B
RUR
REV. 1.0.3
IT
0

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