XRT75R12DIB-F Exar Corporation, XRT75R12DIB-F Datasheet - Page 86
![Peripheral Drivers & Components (PCIs) 12 Channel 3.3V-5V temp -45 to 85C](/photos/16/9/160975/xrt75r12_sml.jpg)
XRT75R12DIB-F
Manufacturer Part Number
XRT75R12DIB-F
Description
Peripheral Drivers & Components (PCIs) 12 Channel 3.3V-5V temp -45 to 85C
Manufacturer
Exar Corporation
Datasheet
1.XRT75R12DIB-F.pdf
(133 pages)
Specifications of XRT75R12DIB-F
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V to 5 V
Package / Case
TBGA-420
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
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C
XRT75R12D
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
B
HANNEL
IT
N
UMBER
1
0
C
ONTROL
STS-1/
SR/DR_n
R
N
EGISTER
AME
DS3
_n
- C
HANNEL N
T
R/W
R/W
YPE
STS-1/DS3 Mode Select - Channel_n:
This READ/WRITE bit-field, along with Bit 2 (E3_n) is used to configure a
given channel into either the DS3, E3 or STS-1 Modes.
This bit-field is ignored if Bit 2 (E3_n) has been set to "1".
If Bit 2 (E3_n) is a 0:
0 - Configures Channel_n to operate in the DS3 Mode.
1 - Configures Channel_n to operate in the STS-1 Mode .
Single-Rail/Dual-Rail Select - Channel_n:
This READ/WRITE bit-field is used to configure Channel_n to operate in
either the Single-Rail or Dual-Rail Mode.
If the user configures the Channel to operate in the Single-Rail Mode, the
following will happen.
•
•
•
•
If the user configures Channel_n to operate in the Dual-Rail Mode, the fol-
lowing will happen.
•
•
•
0 - Configures Channel_n to operate in the Dual-Rail Mode.
1 - Configures Channel_n to operate in the Single-Rail Mode.
A
The B3ZS/HDB3 Encoder and Decoder blocks (within Channel_n) will be
enabled.
The Transmit Section of Channel_n will accept all of the outbound data
(from the System-side Equipment) via the TxPOS_n input pin.
The Receive Section of each channel will output all of the recovered data
(to the System-side Equipment) via the RxPOS_n output pin.
The corresponding RNEG/LCV_n output pin will now function as the LCV
(Line Code Violation or Excessive Zero Event) indicator output pin for
Channel_n.
The B3ZS/HDB3 Encoder and Decoder blocks of Channel_n will be
disabled.
The Transmit Section of Channel_n will be configured to accept positive-
polarity data via the TxPOS_n input pin and negative-polarity data via the
TxNEG_n input pin.
The Receive Section of Channel_n will pulse the RxPOS_n output pin
"High" (for one period of RCLK_n) for each time a positive-polarity pulse is
received via the RTIP_n/RRING_n input pins.
Section of each channel will pulse the RxNEG_n output pin "High" (for
one period of RxCLK_n) for each time a negative-polarity pulse is
received via the RTIP_n/RRING_n input pins.
DDRESS
L
82
OCATION
= 0
XM
6 (
D
ESCRIPTION
M
= 0-5 & 8-D)
Likewise, the Receive
REV. 1.0.3
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