XRT75R12DIB-F Exar Corporation, XRT75R12DIB-F Datasheet - Page 3

• Manufacturer Part Number: XRT75R12DIB-F
• Description: Peripheral Drivers & Components (PCIs) 12 Channel 3.3V-5V temp -45 to 85C
• Manufacturer: Exar Corporation

Specifications of XRT75R12DIB-F

• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V to 5 V
• Package / Case: TBGA-420
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

REV. 1.0.3
GENERAL DESCRIPTION.............................................................................................................. 1
PIN DESCRIPTIONS (BY FUNCTION) ........................................................................................... 3
FUNCTIONAL DESCRIPTION ...................................................................................................... 18
1.0 R3 TECHNOLOGY (RECONFIGURABLE, RELAYLESS REDUNDANCY) ....................................... 18
2.0 CLOCK SYNTHESIZER ....................................................................................................................... 19
3.0 THE RECEIVER SECTION .................................................................................................................. 21
4.0 JITTER ................................................................................................................................................. 27
F
T
F
F
T
F
F
F
F
T
F
F
F
F
T
F
F
F
F
T
IGURE
ABLE
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
IGURE
ABLE
IGURE
IGURE
IGURE
IGURE
ABLE
A
ORDERING INFORMATION .................................................................................................................... 1
F
T
R
S
S
R
C
G
P
G
1.1 NETWORK ARCHITECTURE ......................................................................................................................... 18
2.1 CLOCK DISTRIBUTION ................................................................................................................................. 20
3.1 RECEIVE LINE INTERFACE .......................................................................................................................... 21
3.2 ADAPTIVE GAIN CONTROL (AGC) .............................................................................................................. 21
3.3 RECEIVE EQUALIZER ................................................................................................................................... 22
3.4 CLOCK AND DATA RECOVERY ................................................................................................................... 22
3.5 LOS (LOSS OF SIGNAL) DETECTOR ........................................................................................................... 23
3.6 B3ZS/HDB3 DECODER .................................................................................................................................. 26
4.1 JITTER TOLERANCE ..................................................................................................................................... 27
4.2 JITTER TRANSFER ........................................................................................................................................ 29
EATURES
RANSMIT
PPLICATIONS
YSTEM
YSTEM
OWER
ECEIVE
ECEIVE
LOCK
ENERAL
ROUND
1: L
2: R
3: T
4: I
5: J
3.3.1 RECOMMENDATIONS FOR EQUALIZER SETTINGS .............................................................................................. 22
3.4.1 DATA/CLOCK RECOVERY MODE ............................................................................................................................ 22
3.4.2 TRAINING MODE........................................................................................................................................................ 22
3.5.1 DS3/STS-1 LOS CONDITION ..................................................................................................................................... 23
3.5.2 DISABLING ALOS/DLOS DETECTION ..................................................................................................................... 23
3.5.3 E3 LOS CONDITION:.................................................................................................................................................. 23
3.5.4 INTERFERENCE TOLERANCE.................................................................................................................................. 24
3.5.5 MUTING THE RECOVERED DATA WITH LOS CONDITION:................................................................................... 26
4.1.1 DS3/STS-1 JITTER TOLERANCE REQUIREMENTS ................................................................................................ 27
4.1.2 E3 JITTER TOLERANCE REQUIREMENTS.............................................................................................................. 28
1. B
2. N
3. S
4. C
5. R
6. R
7. ACG/E
8. L
9. L
10. I
11. I
12. R
13. J
14. I
15. I
I
PLICATIONS
NTERFERENCE
TWELVE CHANNEL E3/DS3/STS-1 LINE INTERFACE UNIT WITH SONET DESYNCHRONIZER
-S
-S
NTERFACE
S
IST BY
ITTER
HE
EFERENCE
I
L
P
OSS
OSS OF
LOCK
IMPLIFIED
UPPLY
ETWORK
LOCK
ECEIVE
ECEIVE
NTERFACE
NTERFERENCE
NTERFERENCE
C
IDE
IDE
ITTER
..................................................................................................................................................................... 2
I
INE
NPUT
NPUT
ECEIVER
INS
NTERFACE
ALOS (A
ONTROL
O
A
T
R
............................................................................................................................................................... 1
S
............................................................................................................................................................. 13
P
D
QUALIZER
D
F
MPLITUDE VERSUS
RANSMIT
IN
J
J
ECEIVE
IDE
T
IAGRAM OF THE
ISTRIBUTION
S
P
P
L
S
ITTER
ITTER
OLERANCE
).......................................................................................................................................................................... 23
R
INE
ATH
IGNAL
INS
N
IGNAL
......................................................................................................................................................... 9
B
C
D
EDUNDANCY
UMBER
NALOG
P
LOCK
LOCK
P
ATA OUTPUT AND CODE VIOLATION TIMING
C
I
M
INS
.................................................................................................................................................. 12
NTERFACE
INS
B
C
T
T
HARACTERISTICS
ARGIN
M
M
LOCK
D
O
OLERANCE
OLERANCE FOR
B
D
HARACTERISTICS
I
ARGIN
ARGIN
............................................................................................................................................... 8
D
EFINITION FOR
P
LOCK
UTPUT AND
EFINITION FOR
NPUT AND
............................................................................................................................................ 10
............................................................................................................................................................. 14
LOS) D
IAGRAM OF THE
ERFORMANCE
M
C
D
T
EASUREMENTS
ONGIFURED IN
IAGRAM
EST
D
XRT 75R12D.................................................................................................................................. 1
A
C
T
T
M
RCHITECTURE
IAGRAM
ONNECTION
EST
EST
ECLARATION AND
F
ODULATION
R
OR
ESULTS
T
S
S
R
.......................................................................................................................................... 21
RANSMIT
ET UP FOR
ET UP FOR
E3 .................................................................................................................................... 28
DS3/STS-1 ...................................................................................................................... 28
E3
E3
ECEIVE
....................................................................................................................................... 22
S
TABLE OF CONTENTS
......................................................................................................................... 2
PECIFICATIONS
....................................................................................................................... 2
I
NPUT
AS PER
AS PER
.................................................................................................................................. 27
E3 M
................................................................................................................................. 21
................................................................................................................................. 25
F
.............................................................................................................................. 18
REQUENCY
C
C
C
ODE
DS3/STS-1 ...................................................................................................... 24
E3. ................................................................................................................... 24
LOCK
ONTROL
ITU-T G.775................................................................................................... 24
ONTROL
ITU-T G.775 .................................................................................................. 23
C
LEARANCE
W
C
ITHOUT
.............................................................................................................. 19
IRCUITRY
(J
P
P
........................................................................................................ 26
ITTER
INS
INS
I
T
U
HRESHOLDS FOR A GIVEN SETTING OF
SING
....................................................................................... 3
....................................................................................... 6
T
D
OLERANCE
RIVING THE
SFM ................................................................................ 20
) ........................................................................... 29
M
ICROPROCESSOR
............................................ 19
REQEN (DS3
XRT75R12D
AND
STS-1 A
P
-