AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 117

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADC Input Multiplexer
At the input to the Fusion ADC is a 32:1 multiplexer. Of the 32 input channels, up to 30 are user
definable. Two of these channels are hardwired internally. Channel 31 connects to an internal
temperature diode so the temperature of the Fusion device itself can be monitored. Channel 0 is wired to
the FPGA’s 1.5 V V
internally makes it unnecessary to use an analog I/O to support these functions. The balance of the MUX
inputs are connected to Analog Quads (see the
which Analog Quad inputs are associated with which specific analog MUX channels. The number of
Analog Quads present is device-dependent; refer to the family list in the
of this datasheet for the number of quads per device. Regardless of the number of quads populated in a
device, the internal connections to both V
and 31, respectively. To sample the internal temperature monitor, it must be strobed (similar to the AT
pads). The TMSTBINT pin on the Analog Block macro is the control for strobing the internal temperature
measurement diode.
To determine which channel is selected for conversion, there is a five-pin interface on the Analog Block,
CHNUMBER[4:0], defined in
analog MUX input channels and the analog input pins.
Table 2-39 • Analog MUX Channels
Analog MUX Channel
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
CC
supply, enabling the Fusion device to monitor its own power supply. Doing this
Table 2-40 on page
CC
R e v i s i o n 1
and the internal temperature diode remain on Channels 0
"Analog Quad" section on page
2-102.
Vcc_analog
Signal
AC0
AC1
AC2
AC3
AC4
AC5
AC6
AV0
AV1
AV2
AV3
AV4
AV5
AV6
AT0
AT1
AT2
AT3
AT4
AT5
AT6
Table 2-39
Actel Fusion Family of Mixed Signal FPGAs
shows the correlation between the
"Fusion Family" table on page I
Analog Quad Number
2-84).
Analog Quad 0
Analog Quad 1
Analog Quad 2
Analog Quad 3
Analog Quad 4
Analog Quad 5
Analog Quad 6
Table 2-39
defines
2- 101