AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 53

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-15 • Memory Map for RTC in ACM Register and Description
Voltage Regulator and Power System Monitor (VRPSM)
The VRPSM macro controls the power-up state of the FPGA. The power-up bar (PUB) pin can turn on
the voltage regulator when set to 0. TRST can enable the voltage regulator when deasserted, allowing
the FPGA to power-up when user want access to JTAG ports. The inputs VRINITSTATE and
RTCPSMMATCH come from the flash bits and RTC, and can also power up the FPGA.
Note:
Figure 2-30 • VRPSM Macro
ACMADDR
0x40
0x41
0x42
0x43
0x44
0x48
0x49
0x4A
0x4B
0x4C
0x50
0x51
0x52
0x53
0x54
0x58
*Signals are hardwired internally and do not exist in the macro core.
Register Name
MATCHREG0
MATCHREG1
MATCHREG2
MATCHREG3
MATCHREG4
MATCHBIT0
MATCHBIT1
MATCHBIT2
MATCHBIT3
MATCHBIT4
COUNTER0
COUNTER1
COUNTER2
COUNTER3
COUNTER4
CTRL_STAT
Counter bits 7:0
Counter bits 15:8
Counter bits 23:16
Counter bits 31:24
Counter bits 39:32
Match register bits 7:0
Match register bits 15:8
Match register bits 23:16
Match register bits 31:24
Match register bits 39:32
Individual match bits 7:0
Individual match bits 15:8
Individual match bits 23:16
Individual match bits 31:24
Individual match bits 29:32
Control (write/read) / Status
(read only) register bits
VRPSM
VRPU
VRINITSTATE
RTCPSMMATCH
PUB
TRST*
Description
R e v i s i o n 1
FPGAGOOD
PUCORE
Used to preload the counter to
a specified start point.
The RTC comparison bits
0 – Not matched
1 – Matched
Refer
page 2-36
The output of the XNOR gates
VREN*
Actel Fusion Family of Mixed Signal FPGAs
to
for details.
Use
Table 2-16
on
Default
Value
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
0x00
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