AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 61

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-34 • Flash Memory Block Organization
Table 2-20 • FB Address Bit Allocation ADDR[17:0]
Block
17
Block Organization
0
Sector
140
Flash Memory Block Addressing
Figure 2-34
Each FB is partitioned into sectors, pages, blocks, and bytes. There are 64 sectors in an FB, and each
sector contains 32 pages and 1 spare page. Each page contains 8 data blocks and 1 auxiliary block.
Each data block contains 16 bytes of user data, and the auxiliary block contains 4 bytes of user data.
Addressing for the FB is shown in
When the spare page of a sector is addressed (SPAREPAGE active), ADDR[11:7] are ignored.
When the Auxiliary block is addressed (AUXBLOCK active), ADDR[6:2] are ignored.
Note: The spare page of sector 0 is unavailable for any user data. Writes to this page will return an error,
and reads will return all zeroes.
1
2
12
shows a graphical representation of the flash memory block.
3
1190
4
11
Page 0
Page 1
Page
5
Page 2
Table
Page 3
6
7
2-20.
7
R e v i s i o n 1
Page 31
Spare Page
6
Block
Actel Fusion Family of Mixed Signal FPGAs
Notes:
1 block = 128 bits
1 page = 8 blocks plus the AUX block
1 sector = 33 pages
1 Flash array = 64 sectors
4
3
Byte
0
2- 45