AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 63

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Figure 2-35 • FB Write Waveform
PAGELOSSPROTECT
DATAWIDTH[1:0]
STATUS[1:0]
ADDR[17:0]
WD[31:0]
Access to the FB is controlled by the BUSY signal. The BUSY output is synchronous to the CLK signal.
FB operations are only accepted in cycles where BUSY is logic 0.
Write Operation
Write operations are initiated with the assertion of the WEN signal.
the multiple Write operations.
When a Write operation is initiated to a page that is currently not in the Page Buffer, the FB control logic
will issue a BUSY signal to the user interface while the page is loaded from the FB Array into the Page
Buffer. (Note: The number of clock cycles that the BUSY output is asserted during the load of the Page
Buffer is variable.) After loading the page into the Page Buffer, the addressed data block is loaded from
the Page Buffer into the Block Buffer. Subsequent writes to the same block of the page will incur no busy
cycles. A write to another block in the page will assert BUSY for four cycles (five cycles when PIPE is
asserted), to allow the data to be written to the Page Buffer and have the current block loaded into the
Block Buffer.
Write operations are considered successful as long as the STATUS output is '00'. A non-zero STATUS
indicates that an error was detected during the operation and the write was not performed. Note that the
STATUS output is "sticky"; it is unchanged until another operation is started.
Only one word can be written at a time. Write word width is controlled by the DATAWIDTH bus. Users
are responsible for keeping track of the contents of the Page Buffer and when to program it to the array.
Just like a regular RAM, writing to random addresses is possible. Users can write into the Page Buffer in
any order but will incur additional BUSY cycles. It is not necessary to modify the entire Page Buffer
before saving it to nonvolatile memory.
Write errors include the following:
BUSY
WEN
1. Attempting to write a page that is Overwrite Protected (STATUS = '01'). The write is not
2. Attempting to write to a page that is not in the Page Buffer when Page Loss Protection is enabled
CLK
performed.
(STATUS = '11'). The write is not performed.
D0
A0
D1
A1
R e v i s i o n 1
S0
S1
D2
A2
S2
D3
A3
Actel Fusion Family of Mixed Signal FPGAs
Figure 2-35 on page 2-47
S3
A4
D4
A5
D5
S4
illustrates
S5
D6
A6
2- 47
S6