AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 127

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-45 • ADC Interface Timing
Parameter
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
SUMODE
HDMODE
SUTVC
HDTVC
SUSTC
HDSTC
SUVAREFSEL
HDVAREFSEL
SUCHNUM
HDCHNUM
SUADCSTART
HDADCSTART
CK2QBUSY
CK2QCAL
CK2QVAL
CK2QSAMPLE
CK2QRESULT
CLR2QBUSY
CLR2QCAL
CLR2QVAL
CLR2QSAMPLE
CLR2QRESULT
RECCLR
REMCLR
MPWSYSCLK
FMAXSYSCLK
Commercial Temperature Range Conditions: T
ADC Interface Timing
Mode Pin Setup Time
Mode Pin Hold Time
Clock Divide Control (TVC) Setup Time
Clock Divide Control (TVC) Hold Time
Sample Time Control (STC) Setup Time
Sample Time Control (STC) Hold Time
Voltage Reference Select (VAREFSEL) Setup Time
Voltage Reference Select (VAREFSEL) Hold Time
Channel Select (CHNUMBER) Setup Time
Channel Select (CHNUMBER) Hold Time
Start of Conversion (ADCSTART) Setup Time
Start of Conversion (ADCSTART) Hold Time
Busy Clock-to-Q
Power-Up Calibration Clock-to-Q
Valid Conversion Result Clock-to-Q
Sample Clock-to-Q
Conversion Result Clock-to-Q
Busy Clear-to-Q
Power-Up Calibration Clear-to-Q
Valid Conversion Result Clear-to-Q
Sample Clear-to-Q
Conversion result Clear-to-Q
Recovery Time of Clear
Removal Time of Clear
Clock Minimum Pulse Width for the ADC
Clock Maximum Frequency for the ADC
Description
R e v i s i o n 1
J
= 70°C, Worst-Case VCC = 1.425 V
100.00
0.56
0.26
0.68
0.32
1.58
1.27
0.00
0.67
0.90
0.00
0.75
0.43
1.33
0.63
3.12
0.22
2.53
2.06
2.15
2.41
2.17
2.25
0.00
0.63
4.00
–2
Actel Fusion Family of Mixed Signal FPGAs
100.00
0.64
0.29
0.77
0.36
1.79
1.45
0.00
0.76
1.03
0.00
0.85
0.49
1.51
0.71
3.55
0.25
2.89
2.35
2.45
2.74
2.48
2.56
0.00
0.72
4.00
–1
100.00
0.75
0.34
0.90
0.43
1.71
0.00
0.89
1.21
0.00
1.00
0.57
1.78
0.84
4.17
0.30
3.39
2.76
2.88
3.22
2.91
3.01
0.00
0.84
4.00
Std.
2.11
Units
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
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