AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 220

FPGA - Field Programmable Gate Array 250K System Gates

AFS250-FGG256

Manufacturer Part Number
AFS250-FGG256
Description
FPGA - Field Programmable Gate Array 250K System Gates
Manufacturer
Actel
Datasheet

Specifications of AFS250-FGG256

Processor Series
AFS250
Core
IP Core
Maximum Operating Frequency
1098.9 MHz
Number Of Programmable I/os
114
Data Ram Size
36864
Supply Voltage (max)
1.575 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Development Tools By Supplier
AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
Mounting Style
SMD/SMT
Supply Voltage (min)
1.425 V
Number Of Gates
250 K
Package / Case
FPBGA-256
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Company
Part Number
Manufacturer
Quantity
Price
Part Number:
AFS250-FGG256
Manufacturer:
Actel
Quantity:
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Manufacturer:
ACTEL
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Part Number:
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Quantity:
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Device Architecture
Table 2-144 • Minimum and Maximum DC Input and Output Levels
Figure 2-125 • AC Loading
Table 2-145 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-146 • 2.5 V GTL+
2- 20 4
2.5 V
GTL+
Drive
Strength
33 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.1
Note:
Speed
Grade
Note:
Std.
–1
–2
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
*Measuring point = V
For the derating values at specific junction temperature and voltage supply levels, refer to
page
t
DOUT
0.66
0.56
0.49
Commercial Temperature Range Conditions: T
Worst-Case VCCI = 2.3 V, VREF = 1.0 V
2.5 V GTL+
Gunning Transceiver Logic Plus is a high-speed bus standard (JESD8-3). It provides a differential
amplifier input buffer and an open-drain output buffer. The VCCI pin should be connected to 2.5 V.
3-9.
Min.
–0.3
V
Timing Characteristics
Input High (V)
2.21
1.88
1.65
VIL
VREF – 0.1 VREF + 0.1
t
VREF + 0.1
DP
Max.
V
trip
0.04
0.04
0.03
t
. See
DIN
Table 2-87 on page 2-168
Min.
1.51
1.29
1.13
t
V
PY
Measuring Point* (V)
VIH
Test Point
t
0.43
0.36
0.32
EOUT
Max.
3.6
1.0
V
GTL+
2.25
1.91
1.68
Max.
VOL
t
R e visio n 1
0.6
ZL
V
VTT
J
for a complete table of trip points.
= 70°C, Worst-Case VCC = 1.425 V,
25
10 pF
2.10
1.79
1.57
VOH
Min.
t
VREF (typ.) (V)
ZH
V
1.0
mA
I
33
t
OL
LZ
mA
I
33
OH
t
HZ
VTT (typ.) (V)
Max.
mA
I
124
OSL
1.5
4.48
3.81
3.35
t
ZLS
3
Max.
I
mA
169
OSH
t
4.34
3.69
4.34
ZHS
3
Table 3-7 on
C
LOAD
µA
I
10
IL
10
1
4
Units
(pF)
ns
ns
ns
µA
I
10
IH
2
4

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