AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 221

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-147 • Minimum and Maximum DC Input and Output Levels
Figure 2-126 • AC Loading
Table 2-148 • AC Waveforms, Measuring Points, and Capacitive Loads
Table 2-149 • HSTL Class I
HSTL
Class I
Drive
Strength
8 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
Input Low (V)
VREF – 0.1
Note:
Speed
Grade
Note:
Std.
–1
–2
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
*Measuring point = V
For the derating values at specific junction temperature and voltage supply levels, refer to
page
t
Commercial Temperature Range Conditions: T
Worst-Case VCCI = 1.4 V, VREF = 0.75 V
DOUT
0.66
0.56
0.49
HSTL Class I
High-Speed Transceiver Logic is a general-purpose high-speed 1.5 V bus standard (EIA/JESD8-6).
Fusion devices support Class I. This provides a differential amplifier input buffer and a push-pull output
buffer.
3-9.
Min.
–0.3
V
Timing Characteristics
Input High (V)
VREF + 0.1
3.18
2.70
2.37
VREF – 0.1 VREF + 0.1
t
VIL
DP
Max.
V
trip
0.04
0.04
0.03
t
. See
DIN
Table 2-87 on page 2-168
Measuring Point* (V)
Min.
2.12
1.81
1.59
t
V
PY
VIH
Test Point
t
0.75
0.43
0.36
0.32
EOUT
Max.
3.6
HSTL
Class I
V
3.24
2.75
2.42
R e v i s i o n 1
t
ZL
Max.
VOL
0.4
V
VTT
J
for a complete table of trip points.
= 70°C, Worst-Case VCC = 1.425 V,
50
20 pF
3.14
2.67
2.35
t
VREF (typ.) (V)
VCCI – 0.4
ZH
VOH
Min.
V
0.75
t
LZ
Actel Fusion Family of Mixed Signal FPGAs
mA mA
I
OL
8
t
HZ
I
VTT (typ.) (V)
OH
8
0.75
Max.
mA
I
OSL
5.47
4.66
4.09
t
39
ZLS
3
Max.
I
mA
OSH
32
t
5.38
4.58
4.02
ZHS
3
Table 3-7 on
C
LOAD
µA
I
10
IL
20
1
4
Units
(pF)
ns
ns
ns
µA
2- 205
I
10
IH
2
4