AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 211

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-123 • Minimum and Maximum DC Input and Output Levels
Figure 2-120 • AC Loading
Table 2-124 • AC Waveforms, Measuring Points, and Capacitive Loads
1.5 V
LVCMOS
Drive
Strength
Applicable to Pro I/O Banks
2 mA
4 mA
6 mA
8 mA
12 mA
Applicable to Advanced I/O Banks
2 mA
4 mA
6 mA
8 mA
12 mA
Applicable to Pro I/O Banks
2 mA
Notes:
1. I
2. I
3. Currents are measured at high temperature (100°C junction temperature) and maximum voltage.
4. Currents are measured at 85°C junction temperature.
5. Software default selection highlighted in gray.
Input Low (V)
0
Note:
larger when operating outside recommended ranges.
IL
IH
is the input leakage current per I/O pin over recommended operation conditions where –0.3 V < VIN < VIL.
is the input leakage current per I/O pin over recommended operating conditions VIH < VIN < VCCI. Input current is
*Measuring point = V
1.5 V LVCMOS (JESD8-11)
Low-Voltage CMOS for 1.5 V is an extension of the LVCMOS standard (JESD8-5) used for general-
purpose 1.5 V applications. It uses a 1.5 V input buffer and push-pull output buffer.
Min.
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
–0.3
V
Data Path
Test Point
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI
0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 2
0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 4
0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 6
0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 8
0.35 * VCCI 0.65 * VCCI 1.575 0.25 * VCCI 0.75 * VCCI 12
0.35 * VCCI 0.65 * VCCI
VIL
Max.
Input High (V)
V
trip
. See
1.5
35 pF
Table 2-87 on page 2-168
Min.
V
V
IH
Enable Path
Test Point
Measuring Point* (V)
Max.
3.6
3.6
3.6
3.6
3.6
3.6
V
R = 1 k
0.75
0.25 * VCCI 0.75 * VCCI 2
0.25 * VCCI 0.75 * VCCI 4
0.25 * VCCI 0.75 * VCCI 6
0.25 * VCCI 0.75 * VCCI 8
0.25 * VCCI 0.75 * VCCI 12
0.25 * VCCI 0.75 * V
R e v i s i o n 1
Max.
VOL
V
for a complete table of trip points.
R to VCCI for t
R to GND for t
35 pF for t
5 pF for t
Min.
V
V
OH
VREF (typ.) (V)
CCI
Actel Fusion Family of Mixed Signal FPGAs
HZ
ZH
–
mA mA
/ t
I
OL
2
/ t
LZ
HZ
LZ
ZHS
I
12
12
OH
/ t
/ t
2
4
6
8
2
4
6
8
2
ZH
ZL
/ t
Max.
ZL
mA
I
/ t
OSL
/ t
16
33
39
55
55
16
33
39
55
55
16
ZLS
/ t
ZHS
3
ZLS
Max.
C
mA
I
OSH
13
25
32
66
66
13
25
32
66
66
13
LOAD
3
35
µA
I
(pF)
10
10
10
10
10
10
10
10
10
10
10
IL
1
4
µA
2- 195
I
10
10
10
10
10
10
10
10
10
10
10
IH
2
4