AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 278

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

DC and Power Characteristics
3- 28
Example of Power Calculation
This example considers a shift register with 5,000 storage tiles, including a counter and memory that
stores analog information. The shift register is clocked at 50 MHz and stores and reads information from
a RAM.
The device used is a commercial AFS600 device operating in typical conditions.
The calculation below uses the power calculation methodology previously presented and shows how to
determine the dynamic and static power consumption of resources used in the application.
Also included in the example is the calculation of power consumption in operating, standby, and sleep
modes to illustrate the benefit of power-saving modes.
Global Clock Contribution—P
Logic—Sequential Cells, Combinational Cells, and Routing Net Contributions—P
P
C-CELL
Operating Mode
P
P
P
Standby Mode and Sleep Mode
P
Operating Mode
P
P
P
P
P
P
P
P
P
P
P
P
Standby Mode and Sleep Mode
CLOCK
CLOCK
CLOCK
CLOCK
S-CELL
S-CELL
S-CELL
C-CELL
C-CELL
NET
NET
NET
LOGIC
LOGIC
LOGIC
C-CELL
F
Number of sequential VersaTiles: N
Estimated number of Spines: N
Estimated number of Rows: N
F
Number of sequential VersaTiles: N
Number of combinatorial VersaTiles: N
Estimated toggle rate of VersaTile outputs:
CLK
CLK
, and P
= (N
= (5,000 + 6,000) * (0.1 / 2) * 0.0007 * 50
= 19.25 mW
= P
= 21.13 mW + 4.35 mW + 19.25 mW
= 44.73 mW
= (P
= (0.0128 + 5 * 0.0019 + 313 * 0.00081 + 5,000 * 0.00011) * 50
= 41.28 mW
= 0 W
= N
= 5,000 * (0.00007 + (0.1 / 2) * 0.00029) * 50
= 21.13 mW
= N
= 4.35 mW
= 50 MHz
= 50 MHz
= 6,000 * (0.1 / 2) * 0.00029 * 50
S-CELL
S-CELL
S-CELL
C-CELL
AC1
NET
+ N
+ N
+ P
* (
* (P
SPINE
C-CELL
α
C-CELL
AC5
1
/ 2) * P
* P
+ (
) * (
+ P
α
AC2
1
α
AC7
CLOCK
NET
/ 2) * P
1
+ N
ROW
/ 2) * P
SPINES
* F
ROW
CLK
= 313
S-CELL
S-CELL
AC6
R e visio n 1
AC8
* PAC3 + N
= 5
C-CELL
) * F
* F
= 5,000
= 5,000
α
CLK
CLK
1
= 6,000
= 0.1 (10%)
S-CELL
* P
AC4
) * F
CLK
S-CELL
,