AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 31

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Clock Aggregation
Clock aggregation allows for multi-spine clock domains. A MUX tree provides the necessary flexibility to
allow long lines or I/Os to access domains of one, two, or four global spines. Signal access to the clock
aggregation system is achieved through long-line resources in the central rib, and also through local
resources in the north and south ribs, allowing I/Os to feed directly into the clock system. As
indicates, this access system is contiguous.
There is no break in the middle of the chip for north and south I/O VersaNet access. This is different from
the quadrant clocks, located in these ribs, which only reach the middle of the rib.Refer to the
Global Resources in Actel Fusion Devices
Figure 2-14 • Clock Aggregation Tree Architecture
Tree Node MUX
Global Driver and MUX
Global Spine
Global Rib
application note.
R e v i s i o n 1
I/O Access
Internal Signal Access
Global Signal Access
Actel Fusion Family of Mixed Signal FPGAs
I/O Tiles
Figure 2-14
Using
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