AFS250-FGG256 Actel, AFS250-FGG256 Datasheet - Page 121

• Manufacturer Part Number: AFS250-FGG256
• Description: FPGA - Field Programmable Gate Array 250K System Gates
• Manufacturer: Actel

Specifications of AFS250-FGG256

• Processor Series: AFS250
• Core: IP Core
• Maximum Operating Frequency: 1098.9 MHz
• Number Of Programmable I/os: 114
• Data Ram Size: 36864
• Supply Voltage (max): 1.575 V
• Maximum Operating Temperature: + 70 C
• Minimum Operating Temperature: 0 C
• Development Tools By Supplier: AFS-Eval-Kit, AFS-BRD600, FlashPro 3, FlashPro Lite, Silicon-Explorer II, Silicon-Sculptor 3, SI-EX-TCA
• Mounting Style: SMD/SMT
• Supply Voltage (min): 1.425 V
• Number Of Gates: 250 K
• Package / Case: FPBGA-256
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Table 2-43 • STC Bits Function
Sample time is computed based on the period of ADCCLK.
The second phase is called the distribution phase. During distribution phase, the ADC computes the
equivalent digital value from the value stored in the input capacitor. In this phase, the output signal
SAMPLE goes back to '0', indicating the sample is completed; but the BUSY signal remains '1', indicating
the ADC is still busy for distribution. The distribution time depends strictly on the number of bits. If the
ADC is configured as a 10-bit ADC, then 10 ADCCLK cycles are needed.
distribution time.
The last phase is the post-calibration phase. This is an optional phase. The post-calibration phase takes
two ADCCLK cycles. The output BUSY signal will remain '1' until the post-calibration phase is completed.
If the post-calibration phase is skipped, then the BUSY signal goes to '0' after distribution phase. As soon
as BUSY signal goes to '0', the DATAVALID signal goes to '1', indicating the digital result is available on
the RESULT output signals. DATAVAILD will remain '1' until the next ADCSTART is asserted. Actel
recommends enabling post-calibration to compensate for drift and temperature-dependent effects. This
ensures that the ADC remains consistent over time and with temperature. The post-calibration phase is
enabled by bit 3 of the Mode register.
MODE[3]: Bit 3 of the Mode register, described in
The calculation for the conversion time for the ADC is summarized in
This example shows how to choose the correct settings to achieve the fastest sample time in 10-bit mode
for a system that runs at 66 MHz.
The period of SYSCLK: t
Choosing TVC between 1 and 33 will meet the maximum and minimum period for the ADCCLK
requirement. A higher TVC leads to a higher ADCCLK period.
The minimum TVC is chosen so that t
TVC of 1 can be computed by
Name
STC
t
N: Number of bits
t
t
t
worst case is a period of SYSCLK, t
t
t
t
t
worst case is a period of SYSCLK, t
Example
sync_read
sample
distrib
sync_write
SAMPLE
conv
conv
post-cal
: conversion time
= t
: Distribution time
: Sample time
: Post-calibration time
sync_read
is the sample time
: maximum time for a signal to synchronize with SYSCLK. For calculation purposes, the
: Maximum time for a signal to synchronize with SYSCLK. For calculation purposes, the
t
ADCCLK
+ t
sample
SYSCLK
[7:0]
=
Bits
+ t
4
EQ
×
distrib
= 1/66 MHz = 0.015 µs
(
t
1
16.
post-cal
+
+ t
EQ 14
TVC
distrib
SYSCLK
SYSCLK
post-cal
t
=
Sample time control
distrib
)
and t
×
MODE 3 [ ]
R e v i s i o n 1
describes the post-calibration time.
t
SYSCLK
.
.
+ t
=
post-cal
sync_write
Table 2-41 on page
N t
×
=
×
ADCCLK
can be run faster. The period of ADCCLK with a
(
4
2 t
×
×
(
1
ADCCLK
+
Actel Fusion Family of Mixed Signal FPGAs
1
)
×
Function
)
EQ
0.015 µs
2-104.
15.
=
0.12 µs
EQ 13
describes the
EQ 13
EQ 14
EQ 15
EQ 16
2- 105