PIC18F6722-E/PT Microchip Technology, PIC18F6722-E/PT Datasheet - Page 104

• Manufacturer Part Number: PIC18F6722-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6722-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
• Lead Free Status / Rohs Status: Details

PIC18F8722 FAMILY
7.5.2
Figure 7-2 shows an example of 16-bit Word Write
mode for PIC18F8527/8622/8627/8722 devices. This
mode is used for word-wide memories which includes
some of the EPROM and Flash-type memories. This
mode allows opcode fetches and table reads from all
forms of 16-bit memory and table writes to any type of
word-wide external memories. This method makes a
distinction between TBLWT cycles to even or odd
addresses.
During
(TBLPTR<0> = 0), the TABLAT data is transferred to a
holding latch and the external address data bus is
tri-stated for the data portion of the bus cycle. No write
signals are activated.
FIGURE 7-2:
DS39646C-page 102
Note 1:
a
PIC18F8X27/8X22
16-BIT WORD WRITE MODE
TBLWT
2:
A<19:16>
AD<15:8>
Upper-order address lines are used only for 20-bit address widths.
This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”.
AD<7:0>
cycle
16-BIT WORD WRITE MODE EXAMPLE
WRH
ALE
OE
CE
(1)
to
an
even
address
373
373
During
(TBLPTR<0> = 1), the TABLAT data is presented on
the upper byte of the AD15:AD0 bus. The contents of
the holding latch are presented on the lower byte of the
AD<15:0> bus.
The WRH signal is strobed for each write cycle; the
WRL pin is unused. The signal on the BA0 pin indicates
the Least Significant bit of TBLPTR but it is left
unconnected. Instead, the UB and LB signals are
active to select both bytes. The obvious limitation to
this method is that the table write must be done in pairs
on a specific word boundary to correctly write a word
location.
A<20:1>
D<15:0>
a
TBLWT
Address Bus
Data Bus
Control Lines
D<15:0>
A<x:0>
cycle
CE
© 2008 Microchip Technology Inc.
EPROM Memory
to
OE
JEDEC Word
an
WR
odd
(2)
address