PIC18F6722-E/PT Microchip Technology, PIC18F6722-E/PT Datasheet - Page 440

• Manufacturer Part Number: PIC18F6722-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6722-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
• Lead Free Status / Rohs Status: Details

PIC18F8722 FAMILY
DS39646C-page 438
Bus Collision During Start
Bus Collision for Transmit and Acknowledge ........... 240
Capture/Compare/PWM (All ECCP/CCP
CLKO and I/O .......................................................... 400
Clock Synchronization ............................................. 226
Clock/Instruction Cycle .............................................. 69
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Master Mode (CKE = 0) ..................... 407
Example SPI Master Mode (CKE = 1) ..................... 408
Example SPI Slave Mode (CKE = 0) ....................... 409
Example SPI Slave Mode (CKE = 1) ....................... 410
External Clock (All Modes Except PLL) ................... 398
External Memory Bus for Sleep
External Memory Bus for TBLRD (Extended
External Memory Bus for TBLRD
External Memory Bus for TBLRD with 1 T
Fail-Safe Clock Monitor (FSCM) .............................. 316
First Start Bit Timing ................................................ 234
Full-Bridge PWM Output .......................................... 197
Half-Bridge PWM Output ......................................... 196
High/Low-Voltage Detect Characteristics ................ 395
High-Voltage Detect Operation
I
I
I
I
I
I
I
I
I
I
I
I
I
Low-Voltage Detect Operation (VDIRMAG = 0) ....... 293
Master SSP I
Master SSP I
Parallel Slave Port
Parallel Slave Port (PSP) Read ............................... 160
Parallel Slave Port (PSP) Write ............................... 160
Program Memory Read ............................................ 401
Program Memory Write ............................................ 402
PWM Auto-Shutdown (P1RSEN = 0,
PWM Auto-Shutdown (P1RSEN = 1,
PWM Direction Change ........................................... 199
PWM Direction Change at Near
PWM Output ............................................................ 184
Repeated Start Condition ......................................... 235
2
2
2
2
2
2
2
2
2
2
2
2
2
C Acknowledge Sequence .................................... 239
C Bus Data ............................................................ 411
C Bus Start/Stop Bits ............................................. 411
C Master Mode (7 or 10-Bit Transmission) ........... 237
C Master Mode (7-Bit Reception) .......................... 238
C Slave Mode (10-Bit Reception, SEN = 0) .......... 223
C Slave Mode (10-Bit Reception, SEN = 1) .......... 228
C Slave Mode (10-Bit Transmission) ..................... 224
C Slave Mode (7-bit Reception, SEN = 0) ............. 221
C Slave Mode (7-Bit Reception, SEN = 1) ............ 227
C Slave Mode (7-Bit Transmission) ....................... 222
C Slave Mode General Call Address
C Stop Condition Receive or Transmit Mode ........ 239
Condition (SDAx Only) ..................................... 241
Modules) .......................................................... 405
(Master/Slave) .................................................. 415
(Master/Slave) .................................................. 415
(Microprocessor Mode) ............................ 105, 108
Microcontroller Mode) .............................. 104, 107
(Microprocessor Mode) .................................... 107
Wait State (Microprocessor Mode) .................. 104
(VDIRMAG = 1) ................................................ 294
Sequence (7 or 10-Bit Address Mode) ............. 229
(PIC18F8527/8622/8627/8722) ....................... 406
Auto-Restart Disabled) ..................................... 202
Auto-Restart Enabled) ..................................... 202
100% Duty Cycle ............................................. 199
2
2
C Bus Data ........................................ 413
C Bus Start/Stop Bits ........................ 413
CY
Timing Diagrams and Specifications
Reset, Watchdog Timer (WDT), Oscillator Start-up
Send Break Character Sequence ............................ 263
Slave Synchronization ............................................. 211
Slow Rise Time (MCLR Tied to V
SPI Mode (Master Mode) ......................................... 210
SPI Mode (Slave Mode, CKE = 0) ........................... 212
SPI Mode (Slave Mode, CKE = 1) ........................... 212
Synchronous Reception (Master Mode, SREN) ...... 266
Synchronous Transmission ..................................... 264
Synchronous Transmission (Through TXEN) .......... 265
Time-out Sequence on POR w/PLL Enabled
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Time-out Sequence on Power-up
Timer0 and Timer1 External Clock .......................... 404
Transition for Entry to Idle Mode ................................ 46
Transition for Entry to SEC_RUN Mode .................... 43
Transition for Entry to Sleep Mode ............................ 45
Transition for Two-Speed Start-up
Transition for Wake from Idle to Run Mode ............... 46
Transition for Wake from Sleep (HSPLL) .................. 45
Transition from RC_RUN Mode to
Transition from SEC_RUN Mode to
Transition to RC_RUN Mode ..................................... 44
Typical Opcode Fetch, 8-Bit Mode .......................... 108
A/D Conversion Requirements ................................ 417
AC Characteristics
Capture/Compare/PWM Requirements
CLKO and I/O Requirements ........................... 400, 401
EUSART Synchronous Receive
EUSART Synchronous Transmission
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Mode Requirements
Example SPI Slave Mode Requirements
External Clock Requirements .................................. 398
I
I
Master SSP I
Master SSP I
Parallel Slave Port Requirements
PLL Clock ................................................................ 399
Program Memory Write Requirements .................... 402
2
2
C Bus Data Requirements (Slave Mode) .............. 412
C Bus Start/Stop Bits Requirements
Timer (OST) and Power-up Timer (PWRT) ..... 403
V
(MCLR Tied to V
(MCLR Not Tied to V
(MCLR Not Tied to V
(MCLR Tied to V
(INTOSC to HSPLL) ........................................ 314
PRI_RUN Mode ................................................. 44
PRI_RUN Mode (HSPLL) .................................. 43
Internal RC Accuracy ....................................... 399
(All ECCP/CCP Modules) ................................ 405
Requirements .................................................. 415
Requirements .................................................. 415
(Master Mode, CKE = 0) .................................. 407
(Master Mode, CKE = 1) .................................. 408
(Slave Mode, CKE = 0) .................................... 409
(CKE = 1) ......................................................... 410
(Slave Mode) ................................................... 411
Requirements .................................................. 413
(PIC18F8527/8622/8627/8722) ....................... 406
DD
Rise > T
2
2
C Bus Data Requirements ................ 414
C Bus Start/Stop Bits
PWRT
© 2008 Microchip Technology Inc.
DD
DD
) ............................................ 55
) .......................................... 55
, V
DD
DD
DD
, Case 1) ...................... 54
, Case 2) ...................... 54
Rise < T
DD
,
PWRT
) ........... 54