PIC18F6722-E/PT Microchip Technology, PIC18F6722-E/PT Datasheet - Page 54

• Manufacturer Part Number: PIC18F6722-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6722-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
• Lead Free Status / Rohs Status: Details

PIC18F8722 FAMILY
4.4
The PIC18F8722 family of devices implements a BOR
circuit that provides the user with a number of con-
figuration and power-saving options. The BOR is
controlled by the BORV<1:0> and BOREN<1:0>
Configuration bits. There are a total of four BOR
configurations which are summarized in Table 4-1.
The BOR threshold is set by the BORV<1:0> bits. If
BOR is enabled (any values of BOREN<1:0>, except
‘00’), any drop of V
Section 28.1 “DC Characteristics”) for greater than
T
A Reset may or may not occur if V
for less than T
Reset until V
If the Power-up Timer is enabled, it will be invoked after
V
Reset
(parameter 33, Table 28-12). If V
while the Power-up Timer is running, the chip will go
back into a Brown-out Reset and the Power-up Timer
will be initialized. Once V
Power-up Timer will execute the additional time delay.
BOR
independently configured. Enabling BOR Reset does
not automatically enable the PWRT.
4.4.1
When BOREN<1:0> = 01, the BOR can be enabled or
disabled by the user in software. This is done with the
control bit, SBOREN (RCON<6>). Setting SBOREN
enables the BOR to function as previously described.
Clearing SBOREN disables the BOR entirely. The
SBOREN bit operates only in this mode; otherwise it is
read as ‘0’.
TABLE 4-1:
DS39646C-page 52
BOR
DD
BOREN1
BOR Configuration
rises above V
(parameter 35, Table 28-12) will reset the device.
0
0
1
1
and
for
Brown-out Reset (BOR)
SOFTWARE ENABLED BOR
DD
an
the
BOR
BOREN0
rises above V
BOR CONFIGURATIONS
. The chip will remain in Brown-out
additional
BOR
Power-on
0
1
0
1
DD
below V
; it then will keep the chip in
DD
(RCON<6>)
Unavailable
Unavailable
Unavailable
SBOREN
BOR
Available
Status of
rises above V
time
BOR
Timer
DD
.
DD
drops below V
(parameter D005,
falls below V
delay,
(PWRT)
BOR disabled; must be enabled by reprogramming the Configuration bits.
BOR enabled in software; operation controlled by SBOREN.
BOR enabled in hardware in Run and Idle modes, disabled during
Sleep mode.
BOR enabled in hardware; must be disabled by reprogramming the
Configuration bits.
BOR
T
PWRT
, the
BOR
BOR
are
Placing the BOR under software control gives the user
the additional flexibility of tailoring the application to its
environment without having to reprogram the device to
change the BOR configuration. It also allows the user
to tailor device power consumption in software by
eliminating the incremental current that the BOR con-
sumes. While the BOR current is typically very small, it
may have some impact in low-power applications.
4.4.2
When BOR is enabled, the BOR bit always resets to ‘0’
on any BOR or POR event. This makes it difficult to
determine if a BOR event has occurred just by reading
the state of BOR alone. A more reliable method is to
simultaneously check the state of both POR and BOR.
This assumes that the POR bit is reset to ‘1’ in software
immediately after any POR event. If BOR is ‘0’ while
POR is ‘1’, it can be reliably assumed that a BOR event
has occurred.
4.4.3
When BOREN<1:0> = 10, the BOR remains under
hardware
described. Whenever the device enters Sleep mode,
however, the BOR is automatically disabled. When the
device returns to any other operating mode, BOR is
automatically re-enabled.
This mode allows for applications to recover from
brown-out situations, while actively executing code,
when the device requires BOR protection the most. At
the same time, it saves additional power in Sleep mode
by eliminating the small incremental BOR current.
Note:
BOR Operation
Even when BOR is under software control,
the BOR Reset voltage level is still set by
the BORV<1:0> Configuration bits. It
cannot be changed in software.
DETECTING BOR
DISABLING BOR IN SLEEP MODE
control
and
© 2008 Microchip Technology Inc.
operates
as
previously