PIC18F6722-E/PT Microchip Technology, PIC18F6722-E/PT Datasheet - Page 320

• Manufacturer Part Number: PIC18F6722-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6722-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
• Lead Free Status / Rohs Status: Details

PIC18F8722 FAMILY
TABLE 25-3:
25.5.1
The program memory may be read to or written from
any location using the table read and table write
instructions. The device ID may be read with table
reads. The Configuration registers may be read and
written with the table read and table write instructions.
In normal execution mode, the CPn bits have no direct
effect. CPn bits inhibit external reads and writes. A block
of user memory may be protected from table writes if the
WRTn Configuration bit is ‘0’. The EBTRn bits control
table reads. For a block of user memory with the EBTRn
bit set to ‘0’, a table read instruction that executes from
within that block is allowed to read. A table read instruc-
tion that executes from a location outside of that block is
FIGURE 25-6:
DS39646C-page 318
300008h CONFIG5L
300009h CONFIG5H
30000Ah CONFIG6L
30000Bh CONFIG6H
30000Ch CONFIG7L EBRT7
30000Dh CONFIG7H
Legend: Shaded cells are unimplemented.
Note 1:
File Name
TBLPTR = 0008FFh
Results: All table writes disabled to Blockn whenever WRTn = 0
2:
3:
Register Values
Unimplemented in PIC18F6527/6622/6627/8527/8622/8627 devices; maintain this bit set.
Unimplemented in PIC18F6527/6622/8527/8622 devices; maintain this bit set.
Unimplemented in PIC18F6527/8527 devices; maintain this bit set.
PROGRAM MEMORY
CODE PROTECTION
PC = 00BFFEh
PC = 003FFEh
SUMMARY OF CODE PROTECTION REGISTERS
TABLE WRITE (WRTn) DISALLOWED
WRT7
WRTD
CP7
Bit 7
CPD
—
(1)
(1)
(1)
EBRT6
WRT6
EBTRB
CP6
WRTB
Bit 6
CPB
(1)
(1)
(1)
EBTR5
WRT5
Program Memory
WRTC
CP5
Bit 5
—
—
(2)
TBLWT*
TBLWT*
(2)
(2)
EBTR4
WRT4
CP4
Bit 4
—
—
—
not allowed to read and will result in reading ‘0’s.
Figures 25-6 through 25-8 illustrate table write and table
read protection.
(2)
(2)
Note:
(2)
000000h
0007FFh
000800h
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
.
EBTR3
WRT3
CP3
Bit 3
—
—
—
Code protection bits may only be written to
a ‘0’ from a ‘1’ state. It is not possible to
write a ‘1’ to a bit in the ‘0’ state. Code
protection bits are only set to ‘1’ by a full
chip erase or block erase function. The full
chip erase and block erase functions can
only be initiated via ICSP or an external
programmer.
programming
information.
(3)
(3)
(3)
Configuration Bit Settings
EBTR2
WRT2
Bit 2
CP2
WRTB, EBTRB = 11
WRT0, EBTR0 = 01
WRT1, EBTR1 = 11
WRT2, EBTR2 = 11
WRT3, EBTR3 = 11
—
—
—
© 2008 Microchip Technology Inc.
Refer
specification
EBTR1
WRT1
Bit 1
CP1
—
—
—
to
the
for
EBTR0
WRT0
Bit 0
CP0
—
—
—
device
more