PIC18F6722-E/PT Microchip Technology, PIC18F6722-E/PT Datasheet - Page 55

• Manufacturer Part Number: PIC18F6722-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6722-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
• Lead Free Status / Rohs Status: Details

4.5
The PIC18F8722 family of devices incorporates three
separate on-chip timers that help regulate the Power-on
Reset process. Their main function is to ensure that the
device clock is stable before code is executed. These
timers are:
• Power-up Timer (PWRT)
• Oscillator Start-up Timer (OST)
• PLL Lock Time-out
4.5.1
The Power-up Timer (PWRT) of the PIC18F8722
family of devices is an 11-bit counter which uses the
INTRC source as the clock input. While the PWRT is
counting, the device is held in Reset.
The power-up time delay depends on the INTRC clock
and will vary from chip-to-chip due to temperature and
process variation. See DC parameter 33 in Table 28-12
for details.
The PWRT is enabled by clearing the PWRTEN
Configuration bit.
4.5.2
The Oscillator Start-up Timer (OST) provides a 1024
oscillator cycle (from OSC1 input) delay after the
PWRT delay is over (parameter 33, Table 28-12). This
ensures that the crystal oscillator or resonator has
started and stabilized.
The OST time-out is invoked only for XT, LP, HS and
HSPLL modes and only on Power-on Reset, or on exit
from most power-managed modes.
TABLE 4-2:
© 2008 Microchip Technology Inc.
HSPLL
HS, XT, LP
EC, ECIO
RC, RCIO
INTIO1, INTIO2
Note 1: See parameter 33, Table 28-12.
Configuration
2: 2 ms is the nominal time required for the PLL to lock.
Oscillator
Device Reset Timers
POWER-UP TIMER (PWRT)
OSCILLATOR START-UP TIMER
(OST)
TIME-OUT IN VARIOUS SITUATIONS
T
PWRT
T
PWRT
(1)
PWRTEN = 0
+ 1024 T
T
T
T
(1)
PWRT
PWRT
PWRT
+ 1024 T
Power-up
(1)
(1)
(1)
OSC
+ T
OSC
PLL
(2)
(2)
and Brown-out
4.5.3
With the PLL enabled in its PLL mode, the time-out
sequence following a Power-on Reset is slightly differ-
ent from other oscillator modes. A separate timer is
used to provide a fixed time-out that is sufficient for the
PLL to lock to the main oscillator frequency. This PLL
lock time-out (T
oscillator start-up time-out.
4.5.4
On power-up, the time-out sequence is as follows:
1.
2.
The total time-out will vary based on oscillator configu-
ration and the status of the PWRT. Figure 4-3,
Figure 4-4, Figure 4-5, Figure 4-6 and Figure 4-7 all
depict time-out sequences on power-up, with the
Power-up Timer enabled and the device operating in
HS Oscillator mode. Figures 4-3 through 4-6 also apply
to devices operating in XT or LP modes. For devices in
RC mode and with the PWRT disabled, on the other
hand, there will be no time-out at all.
Since the time-outs occur from the POR pulse, if MCLR
is kept low long enough, all time-outs will expire. Bring-
ing MCLR high will begin execution immediately
(Figure 4-5). This is useful for testing purposes or to
synchronize more than one PIC18F8722 family device
operating in parallel.
1024 T
PIC18F8722 FAMILY
PWRTEN = 1
After the POR pulse has cleared, PWRT time-out
is invoked (if enabled).
Then, the OST is activated.
1024 T
OSC
—
—
—
PLL LOCK TIME-OUT
TIME-OUT SEQUENCE
+ T
OSC
PLL
PLL
(2)
) is typically 2 ms and follows the
Power-Managed Mode
1024 T
1024 T
Exit from
DS39646C-page 53
OSC
—
—
—
+ T
OSC
PLL
(2)