PIC18F6722-E/PT Microchip Technology, PIC18F6722-E/PT Datasheet - Page 439

• Manufacturer Part Number: PIC18F6722-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6722-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
• Lead Free Status / Rohs Status: Details

Sleep
Sleep Mode ........................................................................ 45
Software Simulator (MPLAB SIM) .................................... 372
Special Event Trigger. See Compare (CCP Mode).
Special Event Trigger. See Compare (ECCP Module).
Special Features of the CPU ........................................... 297
Special Function Registers ................................................ 75
SPI Mode (MSSP) ............................................................ 205
SSPOV ............................................................................. 236
SSPOV Status Flag ......................................................... 236
SSPxSTAT Register
SSx .................................................................................. 205
Stack Full/Underflow Resets .............................................. 68
SUBFSR .......................................................................... 367
SUBFWB .......................................................................... 356
SUBLW ............................................................................ 357
SUBULNK ........................................................................ 367
SUBWF ............................................................................ 357
SUBWFB .......................................................................... 358
SWAPF ............................................................................ 358
T
Table Pointer Operations (table) ........................................ 90
Table Reads/Table Writes ................................................. 69
TBLRD ............................................................................. 359
TBLWT ............................................................................. 360
Time-out in Various Situations (table) ................................ 53
Timer0 .............................................................................. 161
© 2008 Microchip Technology Inc.
OSC1 and OSC2 Pin States ...................................... 40
Map ............................................................................ 75
Associated Registers ............................................... 214
Bus Mode Compatibility ........................................... 213
Clock Speed, Interactions ........................................ 213
Effects of a Reset ..................................................... 213
Enabling SPI I/O ...................................................... 209
Master Mode ............................................................ 210
Master/Slave Connection ......................................... 209
Operation ................................................................. 208
Operation in Power-Managed Modes ...................... 213
Serial Clock .............................................................. 205
Serial Data In ........................................................... 205
Serial Data Out ........................................................ 205
Slave Mode .............................................................. 211
Slave Select ............................................................. 205
Slave Select Synchronization .................................. 211
SPI Clock ................................................................. 210
SSPxBUF Register .................................................. 210
SSPxSR Register ..................................................... 210
Typical Connection .................................................. 209
R/W Bit ............................................................. 219, 220
Associated Registers ............................................... 163
Operation ................................................................. 162
Overflow Interrupt .................................................... 163
Prescaler .................................................................. 163
Prescaler Assignment (PSA Bit) .............................. 163
Prescaler Select (T0PS2:T0PS0 Bits) ..................... 163
Prescaler. See Prescaler, Timer0.
Reads and Writes in 16-Bit Mode ............................ 162
Source Edge Select (T0SE Bit) ................................ 162
Source Select (T0CS Bit) ......................................... 162
Switching Prescaler Assignment .............................. 163
Timer1 ............................................................................. 165
Timer2 ............................................................................. 171
Timer3 ............................................................................. 173
Timer4 ............................................................................. 177
Timing Diagrams
PIC18F8722 FAMILY
16-Bit Read/Write Mode .......................................... 167
Associated Registers ............................................... 169
Interrupt ................................................................... 168
Operation ................................................................. 166
Oscillator .......................................................... 165, 167
Overflow Interrupt .................................................... 165
Resetting, Using the CCP
Special Event Trigger (ECCP) ................................. 192
TMR1H Register ...................................................... 165
TMR1L Register ...................................................... 165
Use as a Real-Time Clock ....................................... 168
Associated Registers ............................................... 172
Interrupt ................................................................... 172
Operation ................................................................. 171
Output ...................................................................... 172
PR2 Register ................................................... 184, 192
TMR2 to PR2 Match Interrupt .......................... 184, 192
16-Bit Read/Write Mode .......................................... 175
Associated Registers ............................................... 175
Operation ................................................................. 174
Oscillator .......................................................... 173, 175
Overflow Interrupt ............................................ 173, 175
Special Event Trigger (CCP) ................................... 175
TMR3H Register ...................................................... 173
TMR3L Register ...................................................... 173
Associated Registers ............................................... 178
MSSP Clock Shift .................................................... 178
Operation ................................................................. 177
Postscaler. See Postscaler, Timer4.
PR4 Register ........................................................... 177
Prescaler. See Prescaler, Timer4.
TMR4 Register ........................................................ 177
TMR4 to PR4 Match Interrupt .......................... 177, 178
A/D Conversion ....................................................... 416
Asynchronous Reception ......................................... 261
Asynchronous Transmission ................................... 258
Asynchronous Transmission (Back to Back) ........... 258
Automatic Baud Rate Calculation ............................ 256
Auto-Wake-up Bit (WUE) During
Auto-Wake-up Bit (WUE) During Sleep ................... 262
Baud Rate Generator with Clock Arbitration ............ 233
BRG Overflow Sequence ........................................ 256
BRG Reset Due to SDAx Arbitration
Brown-out Reset (BOR) ........................................... 403
Bus Collision During a Repeated Start
Bus Collision During a Repeated Start
Bus Collision During a Start
Bus Collision During a Stop
Bus Collision During a Stop
Layout Considerations ..................................... 168
Special Event Trigger ...................................... 168
Normal Operation ............................................ 262
During Start Condition ..................................... 242
Condition (Case 1) ........................................... 243
Condition (Case 2) ........................................... 243
Condition (SCLx = 0) ....................................... 242
Condition (Case 1) ........................................... 244
Condition (Case 2) ........................................... 244
DS39646C-page 437