PIC18F6722-E/PT Microchip Technology, PIC18F6722-E/PT Datasheet - Page 106

• Manufacturer Part Number: PIC18F6722-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6722-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
• Lead Free Status / Rohs Status: Details

PIC18F8722 FAMILY
7.5.4
The presentation of control signals on the External
Memory Bus is different for the various operating
modes. Typical signal timing diagrams are shown in
Figure 7-4 through Figure 7-6. All examples assume
either 20-bit or 21-bit address widths.
FIGURE 7-4:
FIGURE 7-5:
DS39646C-page 104
Instruction
AD<15:0>
Execution
A<19:16>
Memory
Instruction
AD<15:0>
Execution
Cycle
A<19:16>
ALE
Memory
OE
CE
Apparent Q
Cycle
16-BIT MODE TIMING
WRH
WRL
BA0
ALE
Actual Q
OE
CE
‘1’
‘1’
‘0’
Q1
EXTERNAL MEMORY BUS TIMING FOR TBLRD WITH A 1 T
(MICROPROCESSOR MODE)
EXTERNAL MEMORY BUS TIMING FOR TBLRD
(EXTENDED MICROCONTROLLER MODE)
Opcode Fetch
INST(PC – 2)
from 000100h
Q1
Q1
Q2
TBLRD *
3AABh
TBLRD Cycle 1
Opcode Fetch
from 007556h
Q2
Q2
MOVLW 55h
Q3
00h
Q4
Q3
Q3
0E55h
Q1
Q4
Q4
TBLRD Cycle 1
Opcode Fetch
from 000102h
MOVLW 55h
Q2
Q1
Q1
Q3
CF33h
Q2
Q2
Q4
Q3
Q3
Q1
from 199E67h
TBLRD Cycle 2
CF33h
Table Read
from 199E67h
TBLRD Cycle 2
TBLRD 92h
of 92h
Q2
Q4
Q4
0Ch
0Ch
Q3
Q4
Q1
9256h
9256h
Q4
1 T
Q4
Q2
© 2008 Microchip Technology Inc.
CY
Q1
Wait
CY
Opcode Fetch
from 000104h
Q4
Q3
ADDLW 55h
WAIT STATE
Q2
MOVLW
Q4
Q4
Q3
‘1’
‘1’
‘0’
Q4