PIC18F6722-E/PT Microchip Technology, PIC18F6722-E/PT Datasheet - Page 46

• Manufacturer Part Number: PIC18F6722-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6722-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
• Lead Free Status / Rohs Status: Details

PIC18F8722 FAMILY
If the IRCF bits and the INTSRC bit are all clear, the
INTOSC output is not enabled and the IOFS bit will
remain clear; there will be no indication of the current
clock source. The INTRC source is providing the
device clocks.
If the IRCF bits are changed from all clear (thus,
enabling the INTOSC output) or if INTSRC is set, the
IOFS bit becomes set after the INTOSC output
becomes stable. Clocks to the device continue while
the INTOSC source stabilizes after an interval of
T
If the IRCF bits were previously at a non-zero value, or
if INTSRC was set before setting SCS1 and the
INTOSC source was already stable, the IOFS bit will
remain set.
FIGURE 3-3:
FIGURE 3-4:
DS39646C-page 44
IOBST
(parameter 39, Table 28-12).
Note 1: Clock transition typically occurs within 2-4 T
Peripheral
Program
Counter
INTRC
OSC1
Clock
Clock
Note1: T
CPU
Multiplexer
CPU Clock
Peripheral
PLL Clock
Program
INTOSC
Counter
Output
2: Clock transition typically occurs within 2-4 T
OSC1
Clock
Q1
OST
SCS1:SCS0 bits Changed
Q2
TRANSITION TIMING TO RC_RUN MODE
PC
TRANSITION TIMING FROM RC_RUN MODE TO PRI_RUN MODE
= 1024 T
Q3
Q4
OSC
Q1
; T
PLL
Q1
1
= 2 ms (approx). These intervals are not shown to scale.
T
OST
(1)
PC
2
Q2
Clock Transition
OSC
3
T
OSTS bit Set
Q3
PLL
.
OSC
(1)
.
(1)
PC + 2
n-1
Q4
On transitions from RC_RUN mode to PRI_RUN mode,
the device continues to be clocked from the INTOSC
multiplexer while the primary clock is started. When the
primary clock becomes ready, a clock switch to the
primary clock occurs (see Figure 3-4). When the clock
switch is complete, the IOFS bit is cleared, the OSTS
bit is set and the primary clock is providing the device
clock. The IDLEN and SCS bits are not affected by the
switch. The INTRC source will continue to run if either
the WDT or the Fail-Safe Clock Monitor is enabled.
n
Q1
1
Transition
2
Clock
n-1 n
(2)
Q2
PC + 2
Q3
Q2
Q4
© 2008 Microchip Technology Inc.
Q3 Q4
Q1
Q1
Q2
PC + 4
PC + 4
Q2
Q3
Q3