PIC18F6722-E/PT Microchip Technology, PIC18F6722-E/PT Datasheet - Page 81

• Manufacturer Part Number: PIC18F6722-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6722-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
• Lead Free Status / Rohs Status: Details

TABLE 5-3:
© 2008 Microchip Technology Inc.
PORTJ
PORTH
PORTG
PORTF
PORTE
PORTD
PORTC
PORTB
PORTA
SPBRGH1
BAUDCON1
SPBRGH2
BAUDCON2
ECCP1DEL
TMR4
PR4
T4CON
CCPR4H
CCPR4L
CCP4CON
CCPR5H
CCPR5L
CCP5CON
SPBRG2
RCREG2
TXREG2
TXSTA2
RCSTA2
ECCP3AS
ECCP3DEL
ECCP2AS
ECCP2DEL
SSP2BUF
SSP2ADD
SSP2STAT
SSP2CON1
SSP2CON2
Legend:
Note
File Name
(2)
(2)
1:
2:
3:
4:
5:
6:
7:
x = unknown, u = unchanged, - = unimplemented, q = value depends on condition
The SBOREN bit is only available when the BOREN<1:0> Configuration bits = 01; otherwise, this bit reads as ‘0’.
These registers and/or bits are not implemented on 64-pin devices and are read as
individual unimplemented bits should be interpreted as ‘-’.
The PLLEN bit is only available in specific oscillator configuration; otherwise, it is disabled and reads as
INTOSC Modes”.
RA6/RA7 and their associated latch and direction bits are individually configured as port pins based on various primary oscillator modes.
When disabled, these bits read as ‘0’.
RG5 and LATG5 are only available when Master Clear is disabled (MCLRE Configuration bit = 0); otherwise, RG5 and LATG5 read as
Bit 7 and Bit 6 are cleared by user software or by a POR.
Bit 21 of TBLPTRU allows access to the device Configuration bits.
EUSART1 Baud Rate Generator Register High Byte
EUSART2 Baud Rate Generator Register High Byte
Timer4 Register
Timer4 Period Register
Capture/Compare/PWM Register 4 High Byte
Capture/Compare/PWM Register 4 Low Byte
Capture/Compare/PWM Register 5 High Byte
Capture/Compare/PWM Register 5 Low Byte
EUSART2 Baud Rate Generator Register Low Byte
EUSART2 Receive Register
EUSART2 Transmit Register
MSSP2 Receive Buffer/Transmit Register
MSSP2 Address Register in I
ECCP3ASE ECCP3AS2 ECCP3AS1 ECCP3AS0
ECCP2ASE ECCP2AS2 ECCP2AS1 ECCP2AS0
ABDOVF
ABDOVF
P1RSEN
P3RSEN
P2RSEN
RA7
WCOL
GCEN
CSRC
SPEN
SMP
Bit 7
RD7
RC7
RH7
RF7
RE7
RB7
RJ7
—
—
—
—
REGISTER FILE SUMMARY (CONTINUED)
(4)
T4OUTPS3
ACKSTAT
SSPOV
P1DC6
P3DC6
P2DC6
RA6
RCIDL
RCIDL
Bit 6
CKE
RH6
RF6
RE6
RD6
RC6
RB6
RX9
RJ6
TX9
—
—
—
(4)
T4OUTPS2
2
C™ Slave mode. MSSP2 Baud Rate Reload Register in I
SSPEN
ACKDT
P1DC5
DC4B1
DC5B1
P3DC5
P2DC5
RG5
SREN
TXEN
Bit 5
RH5
RE5
RD5
RC5
RB5
RA5
RJ5
RF5
D/A
—
—
(5)
T4OUTPS1
ACKEN
P1DC4
DC4B0
DC5B0
P3DC4
P2DC4
SYNC
CREN
SCKP
SCKP
Bit 4
RH4
RG4
RE4
RD4
RC4
RB4
RA4
CKP
RJ4
RF4
P
T4OUTPS0
PSS3AC1
PSS2AC1
CCP4M3
CCP5M3
ADDEN
SENDB
SSPM3
BRG16
BRG16
P1DC3
P3DC3
P2DC3
RCEN
Bit 3
RH3
RG3
RE3
RD3
RC3
RB3
RA3
RJ3
RF3
S
PIC18F8722 FAMILY
PSS3AC0
PSS2AC0
TMR4ON
CCP4M2
CCP5M2
SSPM2
P1DC2
P3DC2
P2DC2
BRGH
FERR
Bit 2
RH2
RG2
RD2
RC2
PEN
RF2
RE2
RB2
RA2
R/W
RJ2
—
—
‘
0
’
. Reset values are shown for 80-pin devices;
T4CKPS1
PSS3BD1
PSS2BD1
CCP4M1
CCP5M1
SSPM1
P1DC1
P3DC1
P2DC1
2
OERR
TRMT
RSEN
C Master mode.
WUE
WUE
Bit 1
RH1
RG1
RD1
RC1
RF1
RE1
RB1
RA1
RJ1
UA
PSS3BD0
PSS2BD0
T4CKPS0
CCP4M0
CCP5M0
ABDEN
ABDEN
SSPM0
P1DC0
P3DC0
P2DC0
TX9D
RX9D
‘
Bit 0
RG0
SEN
RH0
RF0
RE0
RD0
RC0
RB0
RA0
0
RJ0
BF
’
. See Section 2.6.4 “PLL in
DS39646C-page 79
xxxx xxxx
0000 xxxx
--xx xxxx
x000 0000
xxxx xxxx
xxxx xxxx
xxxx xxxx
xxxx xxxx
xx0x 0000
0000 0000
01-0 0-00
0000 0000
01-0 0-00
0000 0000
0000 0000
1111 1111
-000 0000
xxxx xxxx
xxxx xxxx
--00 0000
xxxx xxxx
xxxx xxxx
--00 0000
0000 0000
0000 0000
0000 0000
0000 0010
0000 000x
0000 0000
0000 0000
0000 0000
0000 0000
xxxx xxxx
0000 0000
0000 0000
0000 0000
0000 0000
POR, BOR
Value on
on page:
60, 156
60, 154
60, 151
60, 149
60, 146
60, 143
60, 140
60, 137
61, 135
61, 252
61, 250
61, 252
61, 250
61, 200
61, 178
61, 178
61, 178
61, 180
61, 180
61, 179
61, 180
61, 180
61, 179
61, 252
61, 260
61, 257
61, 248
61, 249
61, 201
61, 200
61, 201
61, 200
61, 170
61, 170
61, 216
61, 217
61, 218
Details
‘
0
’
.