PIC18F6722-E/PT Microchip Technology, PIC18F6722-E/PT Datasheet - Page 208

• Manufacturer Part Number: PIC18F6722-E/PT
• Description: IC,MICROCONTROLLER,8-BIT,PIC CPU,CMOS,TQFP,64PIN,PLASTIC
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F6722-E/PT

• Rohs Compliant: YES
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, HLVD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 128KB (64K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.8K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 12x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 64-TFQFP
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3936 B
• Interface Type: SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 5
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032, DM183022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 12 Channel
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: MA180020 - MODULE PLUG-IN HPC EXPL 18F87J11
• Lead Free Status / Rohs Status: Details

PIC18F8722 FAMILY
19.3.1
Each MSSP module has four registers for SPI mode
operation. These are:
• MSSP Control Register 1 (SSPxCON1)
• MSSP Status Register (SSPxSTAT)
• Serial Receive/Transmit Buffer Register
• MSSP Shift Register (SSPxSR) – Not directly
SSPxCON1 and SSPxSTAT are the control and status
registers in SPI mode operation. The SSPxCON1
register is readable and writable. The lower 6 bits of
the SSPxSTAT are read-only. The upper two bits of the
SSPxSTAT are read/write.
REGISTER 19-1:
DS39646C-page 206
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
(SSPxBUF)
accessible
R/W-0
SMP
REGISTERS
SMP: Sample bit
SPI Master mode:
1 = Input data sampled at end of data output time
0 = Input data sampled at middle of data output time
SPI Slave mode:
SMP must be cleared when SPI is used in Slave mode.
CKE: SPI Clock Select bit
1 = Transmit occurs on transition from active to Idle clock state
0 = Transmit occurs on transition from Idle to active clock state
D/A: Data/Address bit
Used in I
P: Stop bit
Used in I
S: Start bit
Used in I
R/W: Read/Write Information bit
Used in I
UA: Update Address bit
Used in I
BF: Buffer Full Status bit (Receive mode only)
1 = Receive complete, SSPxBUF is full
0 = Receive not complete, SSPxBUF is empty
Note:
R/W-0
CKE
SSPxSTAT: MSSPx STATUS REGISTER (SPI MODE)
2
2
2
2
2
C mode only.
C mode only. This bit is cleared when the MSSP module is disabled, SSPEN is cleared.
C mode only.
C mode only.
C mode only.
Polarity of clock state is set by the CKP bit (SSPxCON1<4>).
W = Writable bit
‘1’ = Bit is set
D/A
R-0
R-0
P
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
SSPxSR is the shift register used for shifting data in or
out. SSPxBUF is the buffer register to which data
bytes are written to or read from.
In receive operations, SSPxSR and SSPxBUF
together create a double-buffered receiver. When
SSPxSR receives a complete byte, it is transferred to
SSPxBUF and the SSPxIF interrupt is set.
During
double-buffered. A write to SSPxBUF will write to both
SSPxBUF and SSPxSR.
R-0
S
transmission,
R/W
R-0
© 2008 Microchip Technology Inc.
x = Bit is unknown
the
R-0
UA
SSPxBUF
R-0
BF
is
bit 0
not