IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 15

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
SOPC Builder Flow
Complete the SOPC Builder System
© March 2009 Altera Corporation
6. Click Finish to complete the DDR and DDR2 SDRAM High-Performance
To complete the SOPC Builder system, follow these steps:
1. In the System Contents tab, select Nios II Processor and click Add.
2. On the Nios II Processor page, in the Core Nios II tab, select altmemddr for Reset
3. Change the Reset Vector Offset and the Exception Vector Offset to an Avalon
Table 2–2. Avalon-MM Addresses for AFI and Non-AFI mode
4. Click Finish.
5. On the System Contents tab, expand Interface Protocols and expand Serial.
6. Select JTAG UART and click Add.
7. Click Finish.
External Memory
Interface Width
f
Controller MegaCore function and add it to the system.
Vector and Exception Vector.
address that is not written to by the ALTMEMPHY megafunction during its
calibration process.
c
To calculate the Avalon-MM address equivalent of the memory address range 0×0
to 0×1f, multiply the memory address by the width of the memory interface data
bus in bytes. For example, if your external memory data width is 8 bits in non-AFI
mode, then the Reset Vector Offset should be 0×20 and the Exception Vector
Offset should be 0x40. Refer to
and non-AFI modes.
1
16
32
64
8
The ALTMEMPHY megafunction performs memory interface calibration
every time it is reset, and in doing so, writes to a range of addresses. If you
want your memory contents to remain intact through a system reset, you
should avoid using these memory addresses. This step is not necessary, if
you reload your SDRAM memory contents from flash every time you reset.
If there are warnings about overlapping addresses, on the System menu,
click Auto Assign Base Addresses.
If you enable ECC and there are warnings about overlapping IRQs, on the
System menu click Auto Assign IRQs.
For detailed explanation of the parameters, refer to the
Settings” on page
0×100
0×200
0×40
0×80
AFI
Reset Vector Offset
3–1.
Table 2–2
DDR and DDR2 SDRAM High-Performance Controller User Guide
Non-AFI
0×100
0×20
0×40
0×80
for more Avalon-MM addresses for AFI
0×120
0×220
0×A0
Exception Vector Offset
0×60
AFI
“Parameter
Non-AFI
0×120
0×40
0×60
0×A0
2–3