IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 23

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
Table 2–4. Files to Compile—VHDL IP Functional Simulation Models (Part 2 of 2)
© March 2009 Altera Corporation
Library
auk_ddr_hp_user_lib
Note for
(1) Applicable only for Arria GX, Arria II GX, Stratix GX, Stratix II GX and Stratix IV devices.
(2) Applicable only for Arria GX, Hardcopy II, Stratix II and Stratix II GX devices.
Table
2–4:
4. Load the testbench in your simulator with the timestep set to picoseconds.
For Verilog HDL simulations with IP functional simulation models, follow these
steps:
1. Create a directory in the <project directory>\testbench directory.
2. Launch your simulation tool from this directory and create the following libraries:
3. Compile the files into the appropriate library as shown in
1
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File Name
<QUARTUS ROOTDIR>/
libraries/vhdl/altera/altera_europa_support_lib.vhd
<project directory>/<variation name>_phy_alt_mem_phy_seq_wrapper.vho
<project directory>/<variation name>_auk_ddr_hp_controller_wrapper.vho
<project directory>/<variation name>_phy.vho
<project directory>/<variation name>.vhd
<project directory>/<variation name>_example_top.vhd
<project directory>/<variation name>_controller_phy.vhd
<project directory>/<variation name>_phy_alt_mem_phy_reconfig.vhd
<project directory>/<variation name>_phy_alt_mem_phy_pll.vhd
<project directory>/<variation name>_phy_alt_mem_phy_seq.vhd
<project directory>/<variation name>_example_driver.vhd
<project directory>/<variation name>_ex_lfsr8.vhd
testbench/<variation name>_example_top_tb.vhd
testbench/<variation name>_mem_model.vhd
altera_mf_ver
lpm_ver
sgate_ver
<device name>_ver
altera_ver
ALTGXB_ver
<device name>_hssi_ver
auk_ddr_hp_user_lib
If you are targeting Stratix IV devices, you need both the Stratix IV and
Stratix III files (stratixiv_atoms and stratixiii_atoms) to simulate in your
simulator, unless you are using NativeLink.
DDR and DDR2 SDRAM High-Performance Controller User Guide
Table 2–5 on page
(2)
2–12.
2–11