IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 73

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Creating A Simulation Testbench Environment
Creating the Example Project
Configuring the DDR2 SDRAM High-Performance Controller
© March 2009 Altera Corporation
1
The design example in this chapter shows you how to use a DDR2 SDRAM high-
performance controller in non-AFI mode with a Cyclone III device, and half-rate
implementation on a Windows-based system. The principles in this design example
are the same for any other mode of the Altera DDR and DDR2 SDRAM high-
performance ALTMEMPHY-based memory controllers.
The Megawizard Plug-In Manager automatically generates an example testbench.
This flow is used as the simplest way to create a complete testbench, including an
example driver, a memory controller, ALTMEMPHY megafunction, and a memory
model.
The DDR and DDR2 SDRAM High-Performance Controller MegaCore functions
include the ability to generate an example testbench, whereas the megafunctions such
as ALTMEMPHY do not.
Follow the
project targeting your chosen device family. This example uses the EP3C40F48C6
device. However, as the example only uses the Quartus II software to generate the
MegaCore variation and launch ModelSim-AE, the specific device is not important.
The example project is created in Verilog HDL although you can substitute with
VHDL. Most memory vendors provide their memory models in Verilog HDL.
ModelSim-AE only simulates a single HDL language at a time. The Altera “generic”
memory model is more memory efficient in Verilog HDL.
Once you have created the example project, launch the Megawizard Plug-In Manager
and follow these steps:
1. Expand the Memory Controllers folder under the Interfaces folder.
2. Click DDR2 SDRAM High-Performance Controller.
3. In the Memory Settings tab on the Parameter Settings page, under General
Settings set the following values:
a. Set the Device family to Cyclone III. (This should already be default.)
b. Set the Speed grade to 6.
c. Select 100 MHz for PLL reference clock frequency.
d. Select 200 MHz for Memory clock frequency.
e. Select Half for Local interface clock frequency.
“MegaWizard Plug-In Manager Flow” on page 2–4
5. Example Design Walkthrough
DDR and DDR2 SDRAM High-Performance Controller User Guide
to create an example