IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 20

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

2–8
Simulate the Example Design
DDR and DDR2 SDRAM High-Performance Controller User Guide
f
9. Set the <variation name>_example_top.v or .vhd file to be the project top-level
10. Simulate the example design (refer to
You can simulate the example design with the MegaWizard Plug-In Manager-
generated IP functional simulation models. The MegaWizard Plug-In Manager
generates a VHDL or Verilog HDL testbench for your example design, which is in the
testbench directory in your project directory.
You can use the IP functional simulation model with any Altera-supported VHDL or
Verilog HDL simulator. You can perform a simulation in a third-party simulation tool
from within the Quartus II software, using NativeLink.
For more information on the testbench, refer to
For more information on NativeLink, refer to the
Simulation Tools
Simulating Using NativeLink
To set up simulation in the Quartus II software using NativeLink, follow these steps:
1. Create a custom variation with an IP functional simulation model, refer to step
2. Set the top-level entity to the example project.
3. Set up the Quartus II NativeLink.
design file.
a. On the File menu, click Open.
b. Browse to <variation name>_example_top and click Open.
c. On the Project menu, click Set as Top-Level Entity.
page
the
a. On the File menu, click Open.
b. Browse to <variation name>_example_top and click Open.
c. On the Project menu, click Set as Top-Level Entity.
a. On the Assignments menu, click Settings. In the Category list, expand EDA
b. From the Tool name list, click on your preferred simulator.
1
c. In NativeLink settings, select Compile test bench and click Test Benches.
d. Click New at the Test Benches page to create a testbench.
Tool Settings and click Simulation.
“Specify Parameters”
2–8) and compile (refer to
Check that the absolute path to your third-party simulator executable is set.
On the Tools menu, click Options and select EDA Tools Options.
chapter in volume 3 of the Quartus II Handbook.
section on
“Compile the Design” on page
page
“Simulate the Example Design” on
2–5.
“Example Design” on page
Simulating Altera IP in Third-Party
© March 2009 Altera Corporation
MegaWizard Plug-In Manager Flow
Chapter 2: Getting Started
2–13).
4–11.
4
in