IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 66

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–38
Table 4–6. Clock and Reset Signals (Part 2 of 2)
DDR and DDR2 SDRAM High-Performance Controller User Guide
oct_ctl_rt_value
dqs_delay_ctrl_import
Name
Direction
Input
Input
ALTMEMPHY signal that specifies the parallel termination value.
Should be connected to the ALT_OCT megafunction output
parallelterminationcontrol.
Allows the use of DLL in another ALTMEMPHY instance in this
ALTMEMPHY instance. Connect the export port on the
ALTMEMPHY instance with a DLL to the import port on the other
ALTMEMPHY instance.
Description
Chapter 4: Functional Description
© March 2009 Altera Corporation
Interfaces and Signals