IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 19

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
Table 2–3. Generated Files (Part 2 of 2)
© March 2009 Altera Corporation
<variation_name>_phy_alt_mem_phy_dq_dqs_clearbox.txt
<variation_name>_phy_alt_mem_phy_pll.qip
<variation_name>_phy_alt_mem_phy_pll.v/.vhd
<variation_name>_phy_alt_mem_phy_pll_bb.v/.cmp
<variation_name>_phy_alt_mem_phy_reconfig.qip
<variation_name>_phy_alt_mem_phy_reconfig.v/.vhd
<variation_name>_phy_alt_mem_phy_reconfig_bb.v/cmp
<variation_name>_phy_alt_mem_phy_seq.vhd
<variation_name>_phy_alt_mem_phy_seq_wrapper.v/.vhd
<variation_name>_phy_alt_mem_phy_seq_wrapper.vo/.vho
<variation_name>_phy_alt_mem_phy.v
<variation_name>_phy_bb.v/.cmp
<variation_name>_phy_ddr_pins.tcl
<variation_name>_phy_ddr_timing.sdc
<variation_name>_phy_report_timing.tcl
<variation_name>_pin_assignments.tcl
Filename
Specification file that generates the
<variation_name>_alt_mem_phy_dq_dqs file using
the clearbox flow. Arria II GX devices only.
Quartus II IP file for the PLL that your ALTMEMPHY
variation uses that contains the files associated with
this megafunction.
The PLL megafunction file for your ALTMEMPHY
variation, generated based on the language you chose
in the MegaWizard Plug-In Manager.
Black box file for the PLL used in your ALTMEMPHY
variation. Typically unused.
Quartus II IP file for the PLL reconfiguration block.
Only generated when targeting Arria GX, Arria II GX,
HardCopy II, Stratix II, and Stratix II GX devices.
PLL reconfiguration block module. Only generated
when targeting Arria GX, Arria II GX, HardCopy II,
Stratix II, and Stratix II GX devices.
Blackbox file for the PLL reconfiguration block. Only
generated when targeting Arria GX, Arria II GX,
HardCopy II, Stratix II, and Stratix II GX devices.
Contains the sequencer used during calibration. This
file is encrypted and is always in VHDL language
regardless of the language you chose in the
MegaWizard Plug-In Manager.
A wrapper file, for compilation only, that calls the
sequencer file, created based on the language you
chose in the MegaWizard Plug-In Manager.
A wrapper file, for simulation only, that calls the
sequencer file, created based on the language you
chose in the MegaWizard Plug-In Manager.
Contains all modules of the ALTMEMPHY variation
except for the sequencer. This file is always in Verilog
HDL language regardless of the language you chose in
the MegaWizard Plug-In Manager.
Black box file for your ALTMEMPHY variation,
depending whether you are using Verilog HDL or VHDL
language.
Contains procedures used in the
<variation_name>_report_timing.tcl file.
Contains timing constraints for your ALTMEMPHY
variation.
Script that reports timing for your ALTMEMPHY
variation during compilation.
Contains I/O standard, drive strength, output enable
grouping, and termination assignments for your
ALTMEMPHY variation. If your top-level design pin
names do not match the default pin names or a
prefixed version, edit the assignments in this file.
DDR and DDR2 SDRAM High-Performance Controller User Guide
Description
2–7