IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 86

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

A–4
DDR and DDR2 SDRAM High-Performance Controller User Guide
Table A–4. Interrupt Mask Register
Table A–5
Table A–5. Single-Bit Error Location Status Register
Table A–6
Table A–6. Double-Bit Error Location Status Register
Bits N – 1 down to 0
Others
Bits N-1 down to 0
Others
Others
Bit
0
1
2
3
4
shows the single-bit error location status register.
shows the double-bit error location status register.
Bit
Bit
Single-bit error
Double-bit error
Maximum single-bit error
Maximum double-bit error
Double-bit error during read-
modify-write
Reserved
Name
Interrupt
Reserved
Cause of Interrupt
Reserved
Name
Name
threshold exceeding condition.
threshold exceeding condition.
occurs during a read-modify-write condition.
(partial write).
Reserved.
When 1, masks single-bit error.
When 1, masks double-bit error.
When 1, masks single-bit error maximum
When 1, masks double-bit error maximum
When 1, masks interrupt when double-bit error
When 0, no single-bit error; when 1, single-bit
error occurred in this 64-bit part.
Reserved.
When 0, no double-bit error; when 1, double-
bit error occurred in this 64-bit part.
Reserved.
Description
Description
Description
© March 2009 Altera Corporation
Register Bits