IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 6

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

1–2
Features
General Description
DDR and DDR2 SDRAM High-Performance Controller User Guide
f
Table 1–2. Device Family Support (Part 2 of 2)
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The Altera DDR and DDR2 SDRAM High-Performance Controller MegaCore
functions provide simplified interfaces to industry-standard DDR SDRAM and DDR2
SDRAM. The MegaCore functions work in conjunction with the Altera ALTMEMPHY
megafunction.
For more information on the ALTMEMPHY megafunction, refer to the
Memory PHY Interface Megafunction User Guide
Stratix
Stratix II GX
Stratix III
Stratix IV
Other device families
Integrated error correction coding (ECC) function
Power-up calibrated on-chip termination (OCT) support for Cyclone III, Stratix III,
and Stratix IV devices
Full-rate and half-rate support
SOPC Builder ready
Support for ALTMEMPHY megafunction
Support for industry-standard DDR and DDR2 SDRAM devices; and registered
and unbuffered DIMMs
Optional support for self-refresh and power-down commands
Optional support for auto-precharge read and auto-precharge write commands
Optional user-controller refresh
Optional Avalon
Optional Altera PHY interface (AFI) Controller-PHY Interface
Optional multiple controller clock sharing in SOPC Builder Flow
Easy-to-use MegaWizard
Support for OpenCore Plus evaluation
Support for the Quartus II IP Advisor
IP functional simulation models for use in Altera-supported VHDL and Verilog
HDL simulators
®
II
Device Family
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Memory-Mapped (Avalon-MM) local interface
TM
interface
Full
Full
Full
Preliminary
No support
(ALTMEMPHY).
Chapter 1: About These MegaCore Functions
© March 2009 Altera Corporation
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