IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 68

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

4–40
Table 4–7. Local Interface Signals (Part 2 of 4)
DDR and DDR2 SDRAM High-Performance Controller User Guide
local_be[]
local_burstbegin
local_read_req
local_refresh_req
local_size[]
local_wdata[]
Signal Name
Direction
Input
Input
Input
Input
Input
Input
Byte enable signal, which you use to mask off individual bytes during writes.
local_be is active high; mem_dm is active low.
To map local_wdata and local_be to mem_dq and mem_dm, consider
a full-rate design with 32-bit local_wdata and 16-bit mem_dq.
Local_wdata = < 22334455 >< 667788AA >< BBCCDDEE >
Local_be
These values map to:
Mem_dq = <4455><2233><88AA><6677><DDEE><BBCC>
Mem_dm = <1 1 ><0 0 ><0 1 ><1 0 ><0 1 ><0 1 >
Avalon burst begin strobe, which indicates the beginning of an Avalon burst.
This signal is only available when the local interface is an Avalon-MM interface
and the memory burst length is greater than 2. Unlike all other Avalon-MM
signals, the burst begin signal does not stay asserted if local_ready is
deasserted.
For write transactions, assert this signal at the beginning of each burst transfer
and keep this signal high for one cycle per burst transfer, even if the slave has
deasserted local_ready. After the slave deasserts local_ready, the
master keeps all the write request signals asserted until local_ready
becomes high again.
For read transactions, assert this signal for one clock cycle when read request
is asserted and the local_address from which the data should be read is
given to the memory. After the slave deasserts local_ready
(waitrequest_n in Avalon), the master keeps all the read request signals
asserted until local_ready becomes high again.
Read request signal.
You cannot assert read request and write request signal at the same time.
User controlled refresh request. If Enable user auto-refresh controls is turned
on, local_refresh_req becomes available and you are responsible for
issuing sufficient refresh requests to meet the memory requirements. This
option allows complete control over when refreshes are issued to the memory
including ganging together multiple refresh commands. Refresh requests take
priority over read and write requests unless they are already being processed.
Controls the number of beats in the requested read or write access to memory,
encoded as a binary number. The range of values depend on the memory burst
length and whether you select full or half rate in the wizard.
If you select a memory burst length 4 and half rate, the local burst length is 1
and so local_size should always be driven with 1.
If you select a memory burst length 4 and full rate, the local burst length is 2
and you should set the local_size to either 1 or 2 for each read or write
request.
Write data bus. The width of local_wdata is twice that of the memory data
bus for a full rate controller; four times the memory data bus for a half rate
controller.
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Chapter 4: Functional Description
© March 2009 Altera Corporation
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