IPR-SDRAM/HPDDR Altera, IPR-SDRAM/HPDDR Datasheet - Page 17

• Manufacturer Part Number: IPR-SDRAM/HPDDR
• Description: IP CORE Renewal Of IP-SDRAM/HPDDR
• Manufacturer: Altera

Specifications of IPR-SDRAM/HPDDR

• Software Application: IP CORE, Memory Controllers, SDRAM
• Supported Families: Stratix FPGAs, Quartus II
• Core Architecture: FPGA
• Core Sub-architecture: Arria, Cyclone, Stratix
• Rohs Compliant: NA
• Lead Free Status / RoHS Status: na

Chapter 2: Getting Started
MegaWizard Plug-In Manager Flow
Specify Parameters
© March 2009 Altera Corporation
To specify DDR or DDR2 SDRAM High-Performance Controller parameters using the
MegaWizard Plug-In Manager flow, follow these steps:
1. In the Quartus II software, create a new Quartus II project with the New Project
2. On the Tools menu, click MegaWizard Plug-In Manager and follow the steps to
3. Specify the parameters on all pages in the Parameter Settings tab.
4. On the EDA tab, turn on Generate simulation model to generate an IP functional
5. On the Summary tab, select the files you want to generate. A gray checkmark
6. Click Finish to generate the MegaCore function and supporting files.
7. If you generate the MegaCore function instance in a Quartus II project, you are
Wizard.
start the MegaWizard Plug-In Manager.
1
f
simulation model for the MegaCore function in the selected language.
An IP functional simulation model is a cycle-accurate VHDL or Verilog HDL
model produced by the Quartus II software.
c
1
indicates a file that is automatically generated. All other files are optional.
f
prompted to add the .qip files to the current Quartus II project. When prompted to
add the .qip files to your project, click Yes. The addition of the .qip files enables
their visibility to Nativelink. Nativelink requires the .qip files to include libraries
for simulation.
1
Use the simulation models only for simulation and not for synthesis or any
other purposes. Using these models for synthesis creates a nonfunctional
design.
The DDR or DDR2 SDRAM High-Performance Controller MegaCore
function is in the Interfaces folder under the Memory Controllers folder.
Some third-party synthesis tools can use a netlist that contains only the
structure of the MegaCore function, but not detailed logic, to optimize
performance of the design that contains the MegaCore function. If your
synthesis tool supports this feature, turn on Generate netlist.
The .qip file is generated by the MegaWizard interface, and contains
information about the generated IP core. In most cases, the .qip file contains
all of the necessary assignments and information required to process the
MegaCore function or system in the Quartus II compiler. The MegaWizard
interface generates a single .qip file for each MegaCore function.
For detailed explanation of the parameters, refer to the
Settings” on page
For more information about the files generated in your project directory,
refer to
Table
2–3.
3–1.
DDR and DDR2 SDRAM High-Performance Controller User Guide
“Parameter
2–5